mirror of
git://projects.qi-hardware.com/ben-wpan.git
synced 2024-12-22 23:42:23 +02:00
great atusd -> atben renaming: renamed design files and some references
- atben/TODO: changed all occurrences of "atusd" to "atben" - atben/TODO: added reminder that the file isn't current anymore - atben/Makefile (NAME): changed project name from "atusd" to "atben" - atben/atusd.brd: renamed to atben/atben.brd - atben/atusd.cmp: renamed to atben/atben.cmp - atben/atusd.pro: renamed to atben/atben.pro - atben/atusd.sch: renamed to atben/atben.sch
This commit is contained in:
parent
3392647574
commit
319bd8345d
12
TODO
12
TODO
@ -1,3 +1,5 @@
|
||||
*** NEEDS UPDATING ***
|
||||
|
||||
General
|
||||
=======
|
||||
|
||||
@ -35,9 +37,9 @@ inside a Ben.
|
||||
|
||||
Update: following Rikard Lindstrom's revelation that we can use the uSD slot
|
||||
also just as general GPIOs, the variant that goes inside the Ben can wait a
|
||||
bit and the atusd board for insertion into the uSD slot is being worked on
|
||||
bit and the atben board for insertion into the uSD slot is being worked on
|
||||
first. We can verify most of the design of a fully integrated board with the
|
||||
atusd board and the latter will be of greater immediate use.
|
||||
atben board and the latter will be of greater immediate use.
|
||||
|
||||
|
||||
Things done
|
||||
@ -50,11 +52,11 @@ Things done
|
||||
- replace discrete balun and filter with integrated solution, to reduce BOM
|
||||
size, maybe cost, insertion loss, and PCB space (see ATRF/ECN0003)
|
||||
|
||||
Done for atusd. At a first glamce, does not seem to affect performance.
|
||||
Done for atben. At a first glamce, does not seem to affect performance.
|
||||
|
||||
- check if we really need three DC blocking caps in the RF path
|
||||
|
||||
Reduced to two in atusd without apparent ill effects.
|
||||
Reduced to two in atben without apparent ill effects.
|
||||
|
||||
|
||||
Things not done yet
|
||||
@ -89,7 +91,7 @@ Things not done yet
|
||||
|
||||
- implement sleep mode
|
||||
|
||||
- (atusd) verify SPI signal timing, particularly the data clock
|
||||
- (atben) verify SPI signal timing, particularly the data clock
|
||||
|
||||
|
||||
ccrf
|
||||
|
@ -1,6 +1,6 @@
|
||||
PLOT_BRD = pcbnew --plot=ps_a4 --ps-pads-drill-opt=none --fill-all-zones
|
||||
|
||||
NAME = atusd
|
||||
NAME = atben
|
||||
|
||||
.PHONY: all gen generate sch brd xpdf front back clean
|
||||
|
||||
|
@ -1,4 +1,4 @@
|
||||
update=Sun Jan 16 19:49:04 2011
|
||||
update=Mon Jan 17 10:53:40 2011
|
||||
last_client=pcbnew
|
||||
[eeschema]
|
||||
version=1
|
Loading…
Reference in New Issue
Block a user