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atusb/fw/include/at86rf230.h: started updates for AT86RF231
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@ -1,8 +1,8 @@
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/*
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* include/at86rf230.h - AT86RF230 protocol and register definitions
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* include/at86rf230.h - AT86RF230/AT86RF231 protocol and register definitions
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*
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* Written 2008-2010 by Werner Almesberger
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* Copyright 2008-2010 Werner Almesberger
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* Written 2008-2011 by Werner Almesberger
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* Copyright 2008-2011 Werner Almesberger
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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@ -34,18 +34,29 @@ enum {
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REG_TRX_STATE = 0x02,
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REG_TRX_CTRL_0 = 0x03,
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REG_TRX_CTRL_1 = 0x04, /* 231 only */
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REG_PHY_TX_PWR = 0x05,
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REG_PHY_RSSI = 0x06,
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REG_PHY_ED_LEVEL = 0x07,
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REG_PHY_CC_CCA = 0x08,
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REG_CCA_THRES = 0x09,
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REG_RX_CTRL = 0x0a, /* 231 only */
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REG_SFD_VALUE = 0x0b, /* 231 only */
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REG_TRX_CTRL_2 = 0x0c, /* 231 only */
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REG_ANT_DIV = 0x0d, /* 231 only */
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REG_IRQ_MASK = 0x0e,
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REG_IRQ_STATUS = 0x0f,
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REG_VREG_CTRL = 0x10,
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REG_BATMON = 0x10,
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REG_XOSC_CTRL = 0x12,
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REG_RX_SYN = 0x15, /* 231 only */
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REG_XAH_CTRL_1 = 0x17, /* 231 only */
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REG_FTN_CTRL = 0x18, /* 231 only */
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REG_PLL_CF = 0x1a,
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REL_PLL_DCU = 0x1b,
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REG_PART_NUM = 0x1c,
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@ -64,9 +75,11 @@ enum {
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REG_IEEE_ADDR_5 = 0x29,
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REG_IEEE_ADDR_6 = 0x2a,
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REG_IEEE_ADDR_7 = 0x2b,
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REG_XAH_CTRL = 0x2c,
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REG_XAH_CTRL_0 = 0x2c, /* XAH_CTRL in 230 */
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REG_CSMA_SEED_0 = 0x2d,
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REG_CSMA_SEED_1 = 0x2e,
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REG_CSMA_BE = 0x2f, /* 231 only */
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REG_CONT_TX_0 = 0x36,
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REG_CONT_TX_1 = 0x3d,
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@ -83,7 +96,7 @@ enum {
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/* --- TRX_STATUS [4:0] ---------------------------------------------------- */
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#define TRX_STATUS_SHIFT 0
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#define TRX_STATUS_MASK 0x0f
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#define TRX_STATUS_MASK 0x1f
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enum {
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TRX_STATUS_P_ON = 0x00, /* reset default */
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@ -100,7 +113,7 @@ enum {
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TRX_STATUS_RX_ON_NOCLK = 0x1c,
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TRX_STATUS_RX_AACK_ON_NOCLK = 0x1d,
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TRX_STATUS_BUSY_RX_AACK_NOCLK = 0x1e,
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TRX_STATUS_TRANSITION = 0x1f
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TRX_STATUS_TRANSITION = 0x1f /* ..._IN_PROGRESS */
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};
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/* --- TRX_STATE [7:5] ----------------------------------------------------- */
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@ -111,6 +124,7 @@ enum {
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enum {
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TRAC_STATUS_SUCCESS = 0, /* reset default */
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TRAC_STATUS_SUCCESS_DATA_PENDING = 1,
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TRAC_STATUS_SUCCESS_WAIT_FOR_ACK = 2, /* 231 only */
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TRAC_STATUS_CHANNEL_ACCESS_FAILURE = 3,
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TRAC_STATUS_NO_ACK = 5,
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TRAC_STATUS_INVALID = 7
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@ -125,6 +139,7 @@ enum {
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TRX_CMD_NOP = 0x00, /* reset default */
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TRX_CMD_TX_START = 0x02,
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TRX_CMD_FORCE_TRX_OFF = 0x03,
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TRX_CMD_FORCE_PLL_ON = 0x04, /* 231 only */
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TRX_CMD_RX_ON = 0x06,
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TRX_CMD_TRX_OFF = 0x08,
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TRX_CMD_PLL_ON = 0x09,
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@ -174,9 +189,28 @@ enum {
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CLKM_CTRL_16MHz = 5
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};
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/* --- TRX_CTRL_1 (231 only) ----------------------------------------------- */
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#define PA_EXT_EN (1 << 8)
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#define IRQ_2_EXT_EN (1 << 7)
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#define TX_AUTO_CRC_ON_231 (1 << 6) /* 231 */
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#define SPI_CMD_MODE_SHIFT 2
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#define SPI_CMD_MODE_MASK 3
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enum {
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SPI_CMD_MODE_EMPTY = 0, /* reset default */
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SPI_CMD_MODE_TRX_STATUS = 1,
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SPI_CMD_MODE_PHY_RSSI = 2,
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SPI_CMD_MODE_IRQ_STATUS = 3,
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};
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#define IRQ_MASK_MODE (1 << 1)
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#define IRQ_POLARITY (1 << 0)
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/* --- PHY_TX_PWR [7] ------------------------------------------------------ */
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#define TX_AUTO_CRC_ON (1 << 7)
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#define TX_AUTO_CRC_ON (1 << 7) /* 230 */
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/* --- PHY_TX_PWR [3:0] ---------------------------------------------------- */
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