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atrf-xtal/atben.c: restructured the code for better clarity; added warnings
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@ -39,12 +39,10 @@
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#define MAX_COUNT (1000*1000)
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static volatile void *base;
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static volatile uint32_t *clkgr;
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static uint32_t old_clkgr;
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/* ----- RF setup ---------------------------------------------------------- */
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void atben_setup(struct atrf_dsc *dsc, int size, int trim)
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static void rf_setup(struct atrf_dsc *dsc, int size, int trim)
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{
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static uint8_t buf[127];
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@ -74,8 +72,67 @@ void atben_setup(struct atrf_dsc *dsc, int size, int trim)
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//atrf_reg_write(dsc, REG_IRQ_MASK, IRQ_TRX_END);
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atrf_reg_write(dsc, REG_IRQ_MASK, 0xff);
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}
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mlockall(MCL_CURRENT);
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/* ----- Ben hardware ------------------------------------------------------ */
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static volatile void *base;
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static volatile uint32_t *icmr, *icmsr, *icmcr;
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static uint32_t old_icmr;
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static volatile uint32_t *clkgr;
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static uint32_t old_clkgr;
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static volatile uint32_t *pdpin, *pddats, *pddatc;
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static void disable_interrupts(void)
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{
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/*
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* @@@ Race condition alert ! If we get interrupted/preempted between
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* reading ICMR and masking all interrupts, and the code that runs
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* between these two operations changes ICMR, then we may set an
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* incorrect mask when restoring interrupts, which may hang the system.
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*/
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old_icmr = *icmr;
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*icmsr = 0xffffffff;
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}
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static void enable_interrupts(void)
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{
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*icmcr = ~old_icmr;
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}
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/*
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* @@@ Disabling the LCD clock will halng operations that depend on the LCD
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* subsystem to advance. This includes the screen saver.
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*/
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static void disable_lcd(void)
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{
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old_clkgr = *clkgr;
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*clkgr = old_clkgr | 1 << 10;
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}
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static void enable_lcd(void)
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{
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*clkgr = old_clkgr;
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}
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static void ben_setup(struct atrf_dsc *dsc)
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{
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/*
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* @@@ Ugly. Should either mmap the registers again here or add some
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* proper means to extract the pointer directly.
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*/
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struct atrf_dsc {
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void *driver;
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@ -88,10 +145,34 @@ void atben_setup(struct atrf_dsc *dsc, int size, int trim)
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};
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base = ((struct atben_dsc *) ((struct atrf_dsc *) dsc)->handle)->mem;
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icmr = base+0x1004;
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icmsr = base+0x1008;
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icmcr = base+0x100c;
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clkgr = base+0x20;
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old_clkgr = *clkgr;
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*clkgr = old_clkgr | 1 << 10;
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pdpin = base+0x10300;
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pddats = base+0x10314;
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pddatc = base+0x10318;
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/*
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* Ironically, switching the LCD clock on and off many times only
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* increases the risk of a hang. Therefore, we leave stop it during
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* all the measurements and only enable it again at the end.
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*/
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disable_lcd();
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}
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/* ----- Interface --------------------------------------------------------- */
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void atben_setup(struct atrf_dsc *dsc, int size, int trim)
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{
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rf_setup(dsc, size, trim);
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mlockall(MCL_CURRENT);
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ben_setup(dsc);
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}
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@ -100,43 +181,45 @@ unsigned atben_sample(struct atrf_dsc *dsc)
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unsigned i = MAX_COUNT;
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(void) atrf_reg_read(dsc, REG_IRQ_STATUS);
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disable_interrupts();
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#if 0
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/*
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* This is a high-level view of what the code should do. It has rather
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* high overhead, though, so we optimize it below.
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*/
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atrf_slp_tr(dsc, 1);
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atrf_slp_tr(dsc, 0);
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while (i) {
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if (atrf_interrupt(dsc))
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break;
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i--;
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}
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#else
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volatile uint32_t *pdpin = base+0x10300;
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volatile uint32_t *pddats = base+0x10314;
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volatile uint32_t *pddatc = base+0x10318;
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volatile uint32_t *icmr = base+0x1004;
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volatile uint32_t *icmsr = base+0x1008;
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volatile uint32_t *icmcr = base+0x100c;
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#if 0
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atrf_slp_tr(dsc, 1);
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while (i) {
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if (*pdpin & 0x1000)
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break;
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i--;
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}
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atrf_slp_tr(dsc, 0);
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#endif
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uint32_t old_icmr = *icmr;
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*icmsr = 0xffffffff;
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/*
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* We hit registers directly. We also don't enforce the upper limit,
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* to squeeze out a few more cycles and gain a finer resolution.
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*/
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/* pulse SLP_TR */
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*pddats = 1 << 9;
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*pddatc = 1 << 9;
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/* count the time until an interrupt arrives */
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do i--;
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while (!(*pdpin & 0x1000));
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*icmcr = ~old_icmr;
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#endif
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enable_interrupts();
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return MAX_COUNT-i;
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}
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void atben_cleanup(struct atrf_dsc *dsc)
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{
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*clkgr = old_clkgr;
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enable_lcd();
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}
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