mirror of
git://projects.qi-hardware.com/ben-wpan.git
synced 2024-11-22 23:55:54 +02:00
atusb: added fab file generation, like in atben
- Makefile (VERSION, DIR): added board version and parent directory name - Makefile: added generation of Gerbers and other fab files - Makefile (gen): this never worked, changed --plot to --plot=ps - Makefile: added section titles - README-PCB: PCB making instructions
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@ -1,15 +1,18 @@
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PLOT_BRD = pcbnew --plot=ps_a4 --ps-pads-drill-opt=none --fill-all-zones
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NAME = atusb
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VERSION = 110214
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DIR = $(NAME)
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.PHONY: all gen generate sch brd xpdf front back clean
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.PHONY: gerber gerbv fab
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all:
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@echo "make what ? target: gen sch brd xpdf front back clean"
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@exit 1
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gen generate:
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eeschema --plot `pwd`/$(NAME).sch
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eeschema --plot=ps `pwd`/$(NAME).sch
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# need scripts
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sch:
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@ -27,6 +30,8 @@ front: $(NAME)-Front.ps
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back: $(NAME)-Back.ps
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lpr $<
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# --- DIY production (toner transfer) -----------------------------------------
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#
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# Postscript for production of front/back layer, using the toner transfer
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# method. Note that other artwork transfer methods may require different
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@ -44,9 +49,39 @@ back: $(NAME)-Back.ps
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%-Back.ps: %.brd
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$(PLOT_BRD) -l Back $<
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# --- Industrial production ---------------------------------------------------
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PCB_FILES = README-PCB $(NAME)-PCB_Edges.dxf $(NAME).drl \
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$(NAME)-SilkS_Front.gto $(NAME)-Mask_Front.gts \
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$(NAME)-Front.gtl $(NAME)-Back.gbl $(NAME)-Mask_Back.gbs \
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$(NAME)-PCB_Edges.gbr
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gerber:
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pcbnew --plot=gerber \
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-l `pcbnew --list-layers $(NAME).brd | tr '\012' ,` \
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--fill-all-zones $(NAME).brd \
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--exclude-pcb-edge
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fab: gerber
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pcbnew --plot=dxf -l PCB_Edges $(NAME).brd
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pcbnew --drill $(NAME).brd
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tar Ccfz .. $(NAME)-$(VERSION).tar.gz $(PCB_FILES:%=$(DIR)/%)
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cd ..; zip -l $(DIR)/$(NAME)-$(VERSION).zip \
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$(PCB_FILES:%=$(DIR)/%)
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gerbv:
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gerbv $(NAME)-Comments.gbr \
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$(NAME)-SilkS_Front.gto \
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$(NAME)-SoldP_Front.gtp \
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$(NAME)-Front.gtl \
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$(NAME)-Mask_Front.gts \
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$(NAME)-Back.gbl
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# --- Cleanup -----------------------------------------------------------------
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clean:
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rm -f $(NAME)-Front.ps $(NAME)-Back.ps
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rm -f $(NAME).drl $(NAME)-PCB_Edges.gbr
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rm -f $(NAME).drl $(NAME)-PCB_Edges.gbr $(NAME)-PCB_Edges.dxf
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rm -f $(NAME)-Front.gtl $(NAME)-Mask_Front.gts
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rm -f $(NAME)-SilkS_Front.gto $(NAME)-SoldP_Front.gtp
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rm -f $(NAME)-Back.gbl $(NAME)-Mask_Back.gbs
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38
atusb/README-PCB
Normal file
38
atusb/README-PCB
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@ -0,0 +1,38 @@
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Board characteristics:
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- stacking: 2 layers, solder mask on front and back, silk screen on front
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- board material: FR4, thickness 0.8 mm, 1 oz copper
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- surface finish: TBD, both ENIG and tin are acceptable
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- via holes: diameter is nominally 10 mil, but any size <= 15 mil can be used
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- mechanical tolerances: <= +/- 0.1 mm on all sides
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Layer stacking, from top to bottom:
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atusb-SilkS_Front.gto Front silk screen
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atusb-Mask_Front.gts Front solder mask
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atusb-Front.gtl Front copper
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atusb-Back.gbl Back copper
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atusb-Mask_Back.gbs Back solder mask (empty)
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Other design files:
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atusb-PCB_Edges.gbr Board edges, for routing (Gerber)
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atusb.dxf idem (AutoCAD DXF)
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atusb.drl Excellon drill file
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Interpretation of files:
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- do not print PCB edges on front/back copper
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- do not print component values on silk screen
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- the center (!) of the board edge line marks the true board edge, e.g.,
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Edge line (5 mil)
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=======
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------- - - - - - ----------
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PCB outside | | PCB inside
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------- - - - - - ----------
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Volume removed when cutting
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(width depends on tool used)
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