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mirror of git://projects.qi-hardware.com/ben-wpan.git synced 2024-11-04 23:23:43 +02:00

atusb: added fab file generation, like in atben

- Makefile (VERSION, DIR): added board version and parent directory name
- Makefile: added generation of Gerbers and other fab files
- Makefile (gen): this never worked, changed --plot to --plot=ps
- Makefile: added section titles
- README-PCB: PCB making instructions
This commit is contained in:
Werner Almesberger 2011-03-12 23:43:00 -03:00
parent 6bbe3bfcf9
commit cdf3825d24
2 changed files with 75 additions and 2 deletions

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@ -1,15 +1,18 @@
PLOT_BRD = pcbnew --plot=ps_a4 --ps-pads-drill-opt=none --fill-all-zones
NAME = atusb
VERSION = 110214
DIR = $(NAME)
.PHONY: all gen generate sch brd xpdf front back clean
.PHONY: gerber gerbv fab
all:
@echo "make what ? target: gen sch brd xpdf front back clean"
@exit 1
gen generate:
eeschema --plot `pwd`/$(NAME).sch
eeschema --plot=ps `pwd`/$(NAME).sch
# need scripts
sch:
@ -27,6 +30,8 @@ front: $(NAME)-Front.ps
back: $(NAME)-Back.ps
lpr $<
# --- DIY production (toner transfer) -----------------------------------------
#
# Postscript for production of front/back layer, using the toner transfer
# method. Note that other artwork transfer methods may require different
@ -44,9 +49,39 @@ back: $(NAME)-Back.ps
%-Back.ps: %.brd
$(PLOT_BRD) -l Back $<
# --- Industrial production ---------------------------------------------------
PCB_FILES = README-PCB $(NAME)-PCB_Edges.dxf $(NAME).drl \
$(NAME)-SilkS_Front.gto $(NAME)-Mask_Front.gts \
$(NAME)-Front.gtl $(NAME)-Back.gbl $(NAME)-Mask_Back.gbs \
$(NAME)-PCB_Edges.gbr
gerber:
pcbnew --plot=gerber \
-l `pcbnew --list-layers $(NAME).brd | tr '\012' ,` \
--fill-all-zones $(NAME).brd \
--exclude-pcb-edge
fab: gerber
pcbnew --plot=dxf -l PCB_Edges $(NAME).brd
pcbnew --drill $(NAME).brd
tar Ccfz .. $(NAME)-$(VERSION).tar.gz $(PCB_FILES:%=$(DIR)/%)
cd ..; zip -l $(DIR)/$(NAME)-$(VERSION).zip \
$(PCB_FILES:%=$(DIR)/%)
gerbv:
gerbv $(NAME)-Comments.gbr \
$(NAME)-SilkS_Front.gto \
$(NAME)-SoldP_Front.gtp \
$(NAME)-Front.gtl \
$(NAME)-Mask_Front.gts \
$(NAME)-Back.gbl
# --- Cleanup -----------------------------------------------------------------
clean:
rm -f $(NAME)-Front.ps $(NAME)-Back.ps
rm -f $(NAME).drl $(NAME)-PCB_Edges.gbr
rm -f $(NAME).drl $(NAME)-PCB_Edges.gbr $(NAME)-PCB_Edges.dxf
rm -f $(NAME)-Front.gtl $(NAME)-Mask_Front.gts
rm -f $(NAME)-SilkS_Front.gto $(NAME)-SoldP_Front.gtp
rm -f $(NAME)-Back.gbl $(NAME)-Mask_Back.gbs

38
atusb/README-PCB Normal file
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@ -0,0 +1,38 @@
Board characteristics:
- stacking: 2 layers, solder mask on front and back, silk screen on front
- board material: FR4, thickness 0.8 mm, 1 oz copper
- surface finish: TBD, both ENIG and tin are acceptable
- via holes: diameter is nominally 10 mil, but any size <= 15 mil can be used
- mechanical tolerances: <= +/- 0.1 mm on all sides
Layer stacking, from top to bottom:
atusb-SilkS_Front.gto Front silk screen
atusb-Mask_Front.gts Front solder mask
atusb-Front.gtl Front copper
atusb-Back.gbl Back copper
atusb-Mask_Back.gbs Back solder mask (empty)
Other design files:
atusb-PCB_Edges.gbr Board edges, for routing (Gerber)
atusb.dxf idem (AutoCAD DXF)
atusb.drl Excellon drill file
Interpretation of files:
- do not print PCB edges on front/back copper
- do not print component values on silk screen
- the center (!) of the board edge line marks the true board edge, e.g.,
Edge line (5 mil)
=======
------- - - - - - ----------
| |
PCB outside | | PCB inside
| |
------- - - - - - ----------
|
Volume removed when cutting
(width depends on tool used)