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mirror of git://projects.qi-hardware.com/ben-wpan.git synced 2024-06-28 22:53:17 +03:00

atben/README-PCB, atusb/README-PCB: various minor clarifications

- README-PCB: added imperial units for board thickness
- README-PCB: changed surface finish recommendation to prefer ENIG more
  strongly
- README-PCB: removed instructions for Gerber file generation from
  "interpretation of files section"
- README-PCB: mention common coordinate system origin
This commit is contained in:
Werner Almesberger 2011-03-14 21:31:55 -03:00
parent 6b3a049003
commit eac6e3c70b
2 changed files with 6 additions and 7 deletions

View File

@ -1,8 +1,8 @@
Board characteristics:
- stacking: 2 layers, solder mask on front and back, silk screen on front
- board material: FR4, thickness 0.8 mm, 1 oz copper
- surface finish: ENIG (preferred) or tin
- board material: FR4, thickness 0.8 mm (1/32"), 1 oz copper
- surface finish: ENIG recommended
- via holes: diameter is nominally 10 mil, but any size <= 15 mil can be used
- mechanical tolerances: <= +/- 0.1 mm on all sides
@ -22,8 +22,7 @@ atben.drl Excellon drill file
Interpretation of files:
- do not print PCB edges on front/back copper
- do not print component values on silk screen
- for all coordinates, the origin is the lower left corner of the board
- the center (!) of the board edge line marks the true board edge, e.g.,
Edge line (5 mil)

View File

@ -1,8 +1,8 @@
Board characteristics:
- stacking: 2 layers, solder mask on front and back, silk screen on front
- board material: FR4, thickness 0.8 mm, 1 oz copper
- surface finish: TBD, both ENIG and tin are acceptable
- board material: FR4, thickness 0.8 mm (1/32"), 1 oz copper
- surface finish: TBD, ENIG is preferred
- via holes: diameter is nominally 10 mil, but any size <= 15 mil can be used
- mechanical tolerances: <= +/- 0.1 mm on all sides
@ -22,7 +22,7 @@ atusb.drl Excellon drill file
Interpretation of files:
- do not print PCB edges on front/back copper
- for all coordinates, the origin is the lower left corner of the board
- do not print component values on silk screen
- the center (!) of the board edge line marks the true board edge, e.g.,