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mirror of git://projects.qi-hardware.com/eda-tools.git synced 2024-12-23 08:02:04 +02:00
eda-tools/boom/lib
Werner Almesberger 2744057e98 Avoid leading zeroes in resistance and capacitance values (except 0R)
- boom/lib/e12.inc: several rules produces mal-formed results with leading
  zeroes
- boom/manu/Makefile.common (spotless): added new target to remove
  $(NAME).chr
- boom/manu/Makefile.common (MALFORMED): test for leading zeroes, allowing
  only 0R as an exception
- boom/manu/stackpole/stackpole.gen: catch values < 1 R and convert them
  to mR
2010-10-18 17:23:19 -03:00
..
ctol.inc For consistency, renamed captol.inc to ctol.inc. Rs now use rtol.inc instead of 2010-10-17 18:26:46 -03:00
e12.inc Avoid leading zeroes in resistance and capacitance values (except 0R) 2010-10-18 17:23:19 -03:00
rtol.inc Added Yageo RT series of precision chip resistors. 2010-10-17 18:19:13 -03:00
tol.inc Added TDK C series of ceramic SMT capacitors. 2010-10-17 03:08:59 -03:00