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Registers and register values are now CPU-specific.

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- fw/common/regs.h: split into C8051F326-specific regs-f326.h and shared
  regs-f32x.h
- fw/common/regs-f320.h: C8051F320-specific registers and values
This commit is contained in:
Werner Almesberger 2010-08-23 14:26:01 -03:00
parent fa7fb48296
commit 1c7150cce8
3 changed files with 86 additions and 10 deletions
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42
fw/common/regs-f320.h Normal file
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@ -0,0 +1,42 @@
/*
* common/regs-f320.h - C8051F320 register definitions
*
* Written 2008 by Werner Almesberger
* Copyright 2008 Werner Almesberger
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef REGS_F320_H
#define REGS_F320_H
#include <mcs51/C8051F326.h>
#include "regs-f32x.h"
/* RSTSRC, extending f32x */
#define WDTRSF 0x08 /* Watchdog Timer Reset Flag */
#define C0RSEF 0x20 /* Comparator0 Reset Enable and Flag */
/* XBR0 */
#define URT0E 0x01 /* UART I/O Output Enable */
#define SPI0E 0x02 /* SPI I/O Enable */
#define SMB0E 0x04 /* SMBus I/O Enable */
#define SYSCKE 0x08 /* nSYSCLK Output Enable */
#define CP0E 0x10 /* Comparator0 Output Enable */
#define CP0AE 0x20 /* Comparator0 Asynchronous Output Enable */
#define CP1E 0x40 /* Comparator1 Output Enable */
#define CP1AE 0x80 /* Comparator1 Asynchronous Output Enable */
/* XBR1 */
#define ECIE 0x08 /* PCA0 External Counter Input Enable */
#define T0E 0x10 /* T0 Enable */
#define T1E 0x20 /* T1 Enable */
#define XBARE 0x40 /* Crossbar Enable */
#define WEAKPUD 0x80 /* Port I/O Weak Pull-up Disable */
#endif /* REGS_F320_H */

36
fw/common/regs-f326.h Normal file
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@ -0,0 +1,36 @@
/*
* common/regs.h - C8051F326 register definitions
*
* Written 2008 by Werner Almesberger
* Copyright 2008 Werner Almesberger
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef REGS_F326_H
#define REGS_F326_H
#include <mcs51/C8051F326.h>
#include "regs-f32x.h"
/* GPIOCN */
#define SYSCLK 0x01 /* nSYSCLK Enable */
#define INPUTEN 0x40 /* Global Digital Input Enable */
#define WEAKPUD 0x80 /* Port I/O Weak Pullup Disable */
/* SMOD0 */
#define S0DL0 0x04 /* Data Length */
#define S0DL1 0x08 /* 00: 5-bit, 01: 6-bit, 10: 7-bit, 11: 8-bit */
/* SBCON0 */
#define SB0PS0 0x01 /* Baud Rate Prescaler Select */
#define SB0PS1 0x02 /* 00: /12, 01: /4, 10: /48, 11: /1 */
#define SB0RUN 0x40 /* Baud Rate Generator Enable */
#define SB0CLK 0x80 /* Baud Rate Clock Source */
#endif /* REGS_F326_H */

18
fw/common/regs.h → fw/common/regs-f32x.h
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@ -1,5 +1,5 @@
/*
* common/regs.h - C8051F326 register definitions
* common/regs-f32x.h - C8051F32x register definitions
*
* Written 2008 by Werner Almesberger
* Copyright 2008 Werner Almesberger
@ -11,10 +11,9 @@
*/
#ifndef REGS_H
#define REGS_H
#ifndef REGS_F32X_H
#define REGS_F32X_H
#include <mcs51/C8051F326.h>
#include "usb-regs.h"
@ -35,6 +34,9 @@
/* OSCICN */
#define IFCN0 0x01 /* Internal Oscillator Frequency Control */
#define IFCN1 0x02 /* 00: /8, 01: /4, 10: /2, 11: /1 */
#define SUSPEND 0x20 /* Force Suspend */
#define IFRDY 0x40 /* Internal Oscillator Frequency Ready Flag */
#define IOSCEN 0x80 /* Internal Oscillator Enable Bit */
/* CLKMUL */
#define MULSEL 0x01 /* Clock Multiplier Input Select */
@ -42,11 +44,6 @@
#define MULINIT 0x40 /* Clock Multiplier Initialize */
#define MULEN 0x80 /* Clock Multiplier Enable */
/* GPIOCN */
#define SYSCLK 0x01 /* nSYSCLK Enable */
#define INPUTEN 0x40 /* Global Digital Input Enable */
#define WEAKPUD 0x80 /* Port I/O Weak Pullup Disable */
/* VDM0CN */
#define VDMEN 0x80 /* VDD Monitor Enable */
#define VDDSTAT 0x40 /* VDD Status */
@ -62,6 +59,7 @@
#define PREN 0x80 /* Internal Pullup Resistor Enable */
/* USB0ADR */
#define AUTORD 0x40 /* USB0 Register Auto-read Flag */
#define BUSY 0x80 /* USB0 Register Read Busy Flag */
/* SMOD0 */
@ -74,4 +72,4 @@
#define SB0RUN 0x40 /* Baud Rate Generator Enable */
#define SB0CLK 0x80 /* Baud Rate Clock Source */
#endif /* REGS_H */
#endif /* REGS_F32X_H */