mirror of
git://projects.qi-hardware.com/f32xbase.git
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d1b3966e5a
- fw/common/regs-f32x.h: common values for TCON, TMOD, and CKCON - fw/common/regs-f320.h: C8051F320-specific values for TMOD and CKCON
100 lines
3.2 KiB
C
100 lines
3.2 KiB
C
/*
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* common/regs-f32x.h - C8051F32x register definitions
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*
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* Written 2008 by Werner Almesberger
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* Copyright 2008 Werner Almesberger
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#ifndef REGS_F32X_H
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#define REGS_F32X_H
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#include "usb-regs.h"
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/* REG0CN */
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#define REGMOD 0x10 /* Voltage Regulator Mode Select */
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#define VBPOL 0x20 /* VBUS Interrupt Polarity Select */
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#define VBSTAT 0x40 /* VBUS Signal Status */
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#define REGDIS 0x80 /* Voltage Regulator Disable */
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/* RSTSRC */
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#define PINRSF 0x01 /* HW Pin Reset Flag */
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/* PORSF 0x02 -- Power-On/VDD Monitor Reset Flag */
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#define MCFRSF 0x04 /* Missing Clock Detector Flag */
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/* SWRSF 0x10 -- Software Reset Force and Flag */
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#define FERROR 0x40 /* Flash Error Indicator */
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#define USBRSF 0x80 /* USB Reset Flag */
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/* OSCICN */
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#define IFCN0 0x01 /* Internal Oscillator Frequency Control */
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#define IFCN1 0x02 /* 00: /8, 01: /4, 10: /2, 11: /1 */
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#define SUSPEND 0x20 /* Force Suspend */
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#define IFRDY 0x40 /* Internal Oscillator Frequency Ready Flag */
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#define IOSCEN 0x80 /* Internal Oscillator Enable Bit */
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/* CLKMUL */
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#define MULSEL 0x01 /* Clock Multiplier Input Select */
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#define MULRDY 0x20 /* Clock Multiplier Ready */
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#define MULINIT 0x40 /* Clock Multiplier Initialize */
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#define MULEN 0x80 /* Clock Multiplier Enable */
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/* VDM0CN */
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#define VDMEN 0x80 /* VDD Monitor Enable */
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#define VDDSTAT 0x40 /* VDD Status */
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/* USB0XCN */
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#define Dn 0x01 /* D- Signal Status */
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#define Dp 0x02 /* D+ Signal Status */
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#define DFREC 0x04 /* Differential Receiver */
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#define PHYTST0 0x08 /* Physical Layer Test */
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#define PHYTST1 0x10 /* 00: normal, 01: "1", 10: "0", 11: SE0 */
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#define SPEED 0x20 /* USB0 Speed Select */
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#define PHYEN 0x40 /* Physical Layer Enable */
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#define PREN 0x80 /* Internal Pullup Resistor Enable */
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/* USB0ADR */
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#define AUTORD 0x40 /* USB0 Register Auto-read Flag */
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#define BUSY 0x80 /* USB0 Register Read Busy Flag */
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/* SMOD0 */
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#define S0DL0 0x04 /* Data Length */
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#define S0DL1 0x08 /* 00: 5-bit, 01: 6-bit, 10: 7-bit, 11: 8-bit */
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/* SBCON0 */
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#define SB0PS0 0x01 /* Baud Rate Prescaler Select */
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#define SB0PS1 0x02 /* 00: /12, 01: /4, 10: /48, 11: /1 */
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#define SB0RUN 0x40 /* Baud Rate Generator Enable */
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#define SB0CLK 0x80 /* Baud Rate Clock Source */
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/* TCON */
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#define IT0 0x01 /* Interrupt 0 Type Select */
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#define IE0 0x02 /* External Interrupt 0 */
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#define IT1 0x04 /* Interrupt 1 Type Select */
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#define IE1 0x08 /* External Interrupt 1 */
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#define TR0 0x10 /* Timer 0 Run Control */
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#define TF0 0x20 /* Timer 0 Overflow Flag */
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#define TR1 0x40 /* Timer 1 Run Control */
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#define TF1 0x80 /* Timer 1 Overflow Flag */
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/* TMOD */
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#define T0M0 0x01 /* Timer 0 Mode Select */
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#define T0M1 0x02
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#define GATE0 0x08 /* Timer 0 Gate Control */
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#define T1M0 0x10 /* Timer 1 Mode Select */
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#define T1M1 0x20
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#define GATE1 0x80 /* Timer 1 Gate Control */
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/* CKCON */
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#define SCA0 0x01 /* Timer 0/1 Prescale Bits */
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#define SCA1 0x02
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#define T0M 0x04 /* Timer 0 Clock Select */
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#define T1M 0x08 /* Timer 0 Clock Select */
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#endif /* REGS_F32X_H */
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