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102 lines
3.2 KiB
C
102 lines
3.2 KiB
C
/*
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* common/usb-regs.h - C8051F326 USB register definitions
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*
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* Written 2008 by Werner Almesberger
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* Copyright 2008 Werner Almesberger
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#ifndef USB_REGS_H
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#define USB_REGS_H
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/* Indirect USB registers */
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#define FADDR 0x00 /* Function Address */
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#define POWER 0x01 /* Power Management */
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#define SUSEN 0x01 /* Suspend Detection Enable */
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#define SUSMD 0x02 /* Suspend Mode */
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#define RESUME 0x04 /* Force Resume */
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#define USBRST 0x08 /* Reset Detect */
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#define USBINH 0x10 /* USB0 Inhibit */
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#define ISOUD 0x80 /* ISO Update */
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#define IN1INT 0x02 /* EP0 and EP1 IN Interrupt Flags */
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#define EP0 0x01 /* EP0 Interrupt-pending Flag */
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#define IN1 0x02 /* IN EP1 Interrupt-pending Flag */
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#define OUT1INT 0x04 /* EP1 OUT Interrupt Flag */
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#define CMINT 0x06 /* Common USB Interrupt Flags */
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#define SUSINT 0x01 /* Suspend Interrupt-Pending Flag */
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#define RSUINT 0x02 /* Resume Interrupt-Pending Flag */
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#define RSTINT 0x04 /* Reset Interrupt-Pending Flag */
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#define SOF 0x08 /* Start of Frame Interrupt */
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#define IN1IE 0x07 /* EP0 and EP1 IN Interrupt Enables */
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#define OUT1IE 0x09 /* EP1 out Interrupt Enable */
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#define CMIE 0x0b /* Common USB Interrupt Enable */
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#define FRAMEL 0x0c /* Frame Number Low Byte */
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#define FRAMEH 0x0d /* Frame Number Low Byte */
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#define INDEX 0x0e /* USB0 EP Index */
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#define CLKREC 0x0f /* Clock Recovery Control */
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#define CRLOW 0x20 /* Low Speed Clock Recovery Mode */
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#define CRSSEN 0x40 /* Clock Recovery Single Step */
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#define CRE 0x80 /* Clock Recovery Enable */
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#define E0CSR 0x11 /* EP0 Control/Status */
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#define OPRDY_0 0x01 /* OUT Packet Ready */
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#define INPRDY_0 0x02 /* IN Packet Ready */
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#define STSTL_0 0x04 /* Sent Stall */
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#define DATAEND 0x08 /* Data End */
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#define SUEND 0x10 /* Setup End */
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#define SDSTL_0 0x20 /* Send Stall */
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#define SOPRDY 0x40 /* Serviced OPRDY */
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#define SSUEND 0x80 /* Serviced Setup End */
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#define EINCSRL 0x11 /* EP IN Control/Status Low Byte */
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#define INPRDY_IN 0x01 /* IN Packet Ready */
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#define FIFONE 0x02 /* FIFO Not Empty */
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#define UNDRUN 0x04 /* Data Underrun */
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#define FLUSH_IN 0x08 /* FIFO Flush */
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#define SDSTL_IN 0x10 /* Send Stall */
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#define STSTL_IN 0x20 /* Sent Stall */
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#define CLRDT_IN 0x40 /* Clear Data Toggle */
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#define EINCSRH 0x12 /* EP OUT Control/Status High Byte */
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#define EOUTCSRL 0x14 /* EP OUT Control/Status Low Byte */
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#define OPRDY_OUT 0x01 /* OUT Packet Ready */
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#define FIFOFUL 0x02 /* OUT FIFO Full */
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#define OVRUN 0x04 /* Data Overrun */
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#define DATERR 0x08 /* Data Error */
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#define FLUSH_OUT 0x10 /* FIFO Flush */
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#define SDSTL_OUT 0x20 /* Send Stall */
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#define STSTL_OUT 0x40 /* Sent Stall */
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#define CLRDT_OUT 0x80 /* Clear Data Toggle */
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#define EOUTCSRH 0x15 /* EP OUT Control/Status High Byte */
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#define E0CNT 0x16 /* Number of Received Bytes in EP0 FIFO */
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#define EOUTCNTL 0x16 /* EP OUT Packet Count Low Byte */
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#define EOUTCNTH 0x17 /* EP OUT Packet Count High Byte */
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#define FIFO0 0x20 /* EP0 FIFO */
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#define FIFO1 0x21 /* EP1 FIFO */
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#endif /* !USB_REGS_H */
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