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f32xbase/fw/common/regs-f320.h
Werner Almesberger d1b3966e5a Added timer register values.
- fw/common/regs-f32x.h: common values for TCON, TMOD, and CKCON
- fw/common/regs-f320.h: C8051F320-specific values for TMOD and CKCON
2010-08-23 18:11:51 -03:00

52 lines
1.6 KiB
C

/*
* common/regs-f320.h - C8051F320 register definitions
*
* Written 2008 by Werner Almesberger
* Copyright 2008 Werner Almesberger
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef REGS_F320_H
#define REGS_F320_H
#include <mcs51/C8051F320.h>
#include "regs-f32x.h"
/* RSTSRC, extending f32x */
#define WDTRSF 0x08 /* Watchdog Timer Reset Flag */
#define C0RSEF 0x20 /* Comparator0 Reset Enable and Flag */
/* XBR0 */
#define URT0E 0x01 /* UART I/O Output Enable */
#define SPI0E 0x02 /* SPI I/O Enable */
#define SMB0E 0x04 /* SMBus I/O Enable */
#define SYSCKE 0x08 /* nSYSCLK Output Enable */
#define CP0E 0x10 /* Comparator0 Output Enable */
#define CP0AE 0x20 /* Comparator0 Asynchronous Output Enable */
#define CP1E 0x40 /* Comparator1 Output Enable */
#define CP1AE 0x80 /* Comparator1 Asynchronous Output Enable */
/* XBR1 */
#define ECIE 0x08 /* PCA0 External Counter Input Enable */
#define T0E 0x10 /* T0 Enable */
#define T1E 0x20 /* T1 Enable */
#define XBARE 0x40 /* Crossbar Enable */
#define WEAKPUD 0x80 /* Port I/O Weak Pull-up Disable */
/* TMOD, extending f32x */
#define C_T0 0x04 /* Counter/Timer Select */
/* CKCON, extending f32x */
#define T2ML 0x10 /* Timer 2 Low Byte Clock Select */
#define T2MH 0x20 /* Timer 2 High Byte Clock Select */
#define T3ML 0x40 /* Timer 3 Low Byte Clock Select */
#define T3MH 0x80 /* Timer 3 High Byte Clock Select */
#endif /* REGS_F320_H */