mirror of
git://projects.qi-hardware.com/f32xbase.git
synced 2024-11-05 13:32:29 +02:00
d1b3966e5a
- fw/common/regs-f32x.h: common values for TCON, TMOD, and CKCON - fw/common/regs-f320.h: C8051F320-specific values for TMOD and CKCON
100 lines
3.2 KiB
C
100 lines
3.2 KiB
C
/*
|
|
* common/regs-f32x.h - C8051F32x register definitions
|
|
*
|
|
* Written 2008 by Werner Almesberger
|
|
* Copyright 2008 Werner Almesberger
|
|
*
|
|
* This program is free software; you can redistribute it and/or modify
|
|
* it under the terms of the GNU General Public License as published by
|
|
* the Free Software Foundation; either version 2 of the License, or
|
|
* (at your option) any later version.
|
|
*/
|
|
|
|
|
|
#ifndef REGS_F32X_H
|
|
#define REGS_F32X_H
|
|
|
|
#include "usb-regs.h"
|
|
|
|
|
|
/* REG0CN */
|
|
#define REGMOD 0x10 /* Voltage Regulator Mode Select */
|
|
#define VBPOL 0x20 /* VBUS Interrupt Polarity Select */
|
|
#define VBSTAT 0x40 /* VBUS Signal Status */
|
|
#define REGDIS 0x80 /* Voltage Regulator Disable */
|
|
|
|
/* RSTSRC */
|
|
#define PINRSF 0x01 /* HW Pin Reset Flag */
|
|
/* PORSF 0x02 -- Power-On/VDD Monitor Reset Flag */
|
|
#define MCFRSF 0x04 /* Missing Clock Detector Flag */
|
|
/* SWRSF 0x10 -- Software Reset Force and Flag */
|
|
#define FERROR 0x40 /* Flash Error Indicator */
|
|
#define USBRSF 0x80 /* USB Reset Flag */
|
|
|
|
/* OSCICN */
|
|
#define IFCN0 0x01 /* Internal Oscillator Frequency Control */
|
|
#define IFCN1 0x02 /* 00: /8, 01: /4, 10: /2, 11: /1 */
|
|
#define SUSPEND 0x20 /* Force Suspend */
|
|
#define IFRDY 0x40 /* Internal Oscillator Frequency Ready Flag */
|
|
#define IOSCEN 0x80 /* Internal Oscillator Enable Bit */
|
|
|
|
/* CLKMUL */
|
|
#define MULSEL 0x01 /* Clock Multiplier Input Select */
|
|
#define MULRDY 0x20 /* Clock Multiplier Ready */
|
|
#define MULINIT 0x40 /* Clock Multiplier Initialize */
|
|
#define MULEN 0x80 /* Clock Multiplier Enable */
|
|
|
|
/* VDM0CN */
|
|
#define VDMEN 0x80 /* VDD Monitor Enable */
|
|
#define VDDSTAT 0x40 /* VDD Status */
|
|
|
|
/* USB0XCN */
|
|
#define Dn 0x01 /* D- Signal Status */
|
|
#define Dp 0x02 /* D+ Signal Status */
|
|
#define DFREC 0x04 /* Differential Receiver */
|
|
#define PHYTST0 0x08 /* Physical Layer Test */
|
|
#define PHYTST1 0x10 /* 00: normal, 01: "1", 10: "0", 11: SE0 */
|
|
#define SPEED 0x20 /* USB0 Speed Select */
|
|
#define PHYEN 0x40 /* Physical Layer Enable */
|
|
#define PREN 0x80 /* Internal Pullup Resistor Enable */
|
|
|
|
/* USB0ADR */
|
|
#define AUTORD 0x40 /* USB0 Register Auto-read Flag */
|
|
#define BUSY 0x80 /* USB0 Register Read Busy Flag */
|
|
|
|
/* SMOD0 */
|
|
#define S0DL0 0x04 /* Data Length */
|
|
#define S0DL1 0x08 /* 00: 5-bit, 01: 6-bit, 10: 7-bit, 11: 8-bit */
|
|
|
|
/* SBCON0 */
|
|
#define SB0PS0 0x01 /* Baud Rate Prescaler Select */
|
|
#define SB0PS1 0x02 /* 00: /12, 01: /4, 10: /48, 11: /1 */
|
|
#define SB0RUN 0x40 /* Baud Rate Generator Enable */
|
|
#define SB0CLK 0x80 /* Baud Rate Clock Source */
|
|
|
|
/* TCON */
|
|
#define IT0 0x01 /* Interrupt 0 Type Select */
|
|
#define IE0 0x02 /* External Interrupt 0 */
|
|
#define IT1 0x04 /* Interrupt 1 Type Select */
|
|
#define IE1 0x08 /* External Interrupt 1 */
|
|
#define TR0 0x10 /* Timer 0 Run Control */
|
|
#define TF0 0x20 /* Timer 0 Overflow Flag */
|
|
#define TR1 0x40 /* Timer 1 Run Control */
|
|
#define TF1 0x80 /* Timer 1 Overflow Flag */
|
|
|
|
/* TMOD */
|
|
#define T0M0 0x01 /* Timer 0 Mode Select */
|
|
#define T0M1 0x02
|
|
#define GATE0 0x08 /* Timer 0 Gate Control */
|
|
#define T1M0 0x10 /* Timer 1 Mode Select */
|
|
#define T1M1 0x20
|
|
#define GATE1 0x80 /* Timer 1 Gate Control */
|
|
|
|
/* CKCON */
|
|
#define SCA0 0x01 /* Timer 0/1 Prescale Bits */
|
|
#define SCA1 0x02
|
|
#define T0M 0x04 /* Timer 0 Clock Select */
|
|
#define T1M 0x08 /* Timer 0 Clock Select */
|
|
|
|
#endif /* REGS_F32X_H */
|