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git://projects.qi-hardware.com/f32xbase.git
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d1b3966e5a
- fw/common/regs-f32x.h: common values for TCON, TMOD, and CKCON - fw/common/regs-f320.h: C8051F320-specific values for TMOD and CKCON
52 lines
1.6 KiB
C
52 lines
1.6 KiB
C
/*
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* common/regs-f320.h - C8051F320 register definitions
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*
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* Written 2008 by Werner Almesberger
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* Copyright 2008 Werner Almesberger
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#ifndef REGS_F320_H
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#define REGS_F320_H
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#include <mcs51/C8051F320.h>
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#include "regs-f32x.h"
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/* RSTSRC, extending f32x */
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#define WDTRSF 0x08 /* Watchdog Timer Reset Flag */
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#define C0RSEF 0x20 /* Comparator0 Reset Enable and Flag */
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/* XBR0 */
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#define URT0E 0x01 /* UART I/O Output Enable */
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#define SPI0E 0x02 /* SPI I/O Enable */
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#define SMB0E 0x04 /* SMBus I/O Enable */
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#define SYSCKE 0x08 /* nSYSCLK Output Enable */
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#define CP0E 0x10 /* Comparator0 Output Enable */
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#define CP0AE 0x20 /* Comparator0 Asynchronous Output Enable */
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#define CP1E 0x40 /* Comparator1 Output Enable */
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#define CP1AE 0x80 /* Comparator1 Asynchronous Output Enable */
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/* XBR1 */
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#define ECIE 0x08 /* PCA0 External Counter Input Enable */
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#define T0E 0x10 /* T0 Enable */
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#define T1E 0x20 /* T1 Enable */
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#define XBARE 0x40 /* Crossbar Enable */
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#define WEAKPUD 0x80 /* Port I/O Weak Pull-up Disable */
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/* TMOD, extending f32x */
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#define C_T0 0x04 /* Counter/Timer Select */
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/* CKCON, extending f32x */
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#define T2ML 0x10 /* Timer 2 Low Byte Clock Select */
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#define T2MH 0x20 /* Timer 2 High Byte Clock Select */
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#define T3ML 0x40 /* Timer 3 Low Byte Clock Select */
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#define T3MH 0x80 /* Timer 3 High Byte Clock Select */
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#endif /* REGS_F320_H */
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