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working on lcd

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This commit is contained in:
Bas Wijnen
2009-06-10 21:42:01 +02:00
parent 9a7abe2fd5
commit 1bb67efc75
9 changed files with 4470 additions and 266 deletions
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293
boot-programs/gpio.txt
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@@ -183,131 +183,168 @@ do { \
// Pins on the trendtac:
0 keyboard
1 keyboard
2 keyboard
3 keyboard
4 keyboard
5 keyboard
6 keyboard
7 keyboard
8 keyboard interrupt
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13 touchpad right button
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109 keyboard
110 keyboard
111 keyboard
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0.00 keyboard
0.01 keyboard
0.02 keyboard
0.03 keyboard
0.04 keyboard
0.05 keyboard
0.06 keyboard
0.07 keyboard
0.08 keyboard interrupt?
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0.13 touchpad right button
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0.16 touchpad left button
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2.00 SPEN: lcd enable
2.01 SPCK: lcd clock
2.02 SPDA: lcd data
2.03 LCD_RET: lcd reset
2.04
2.05
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2.30 PWM enable (for lcd backlight)
2.31
3.00 keyboard
3.01 keyboard
3.02 keyboard
3.03 keyboard
3.04 keyboard
3.05 keyboard
3.06 keyboard
3.07 keyboard
3.08 keyboard
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3.10 keyboard
3.11 keyboard
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Devices enabled in linux:
+ __harb_usb0_uhc();
+ __gpio_as_emc();
+ __gpio_as_uart0();
+ __gpio_as_dma();
+ __gpio_as_eth();
+ __gpio_as_usb();
+ __gpio_as_lcd_master();
+#if defined(CONFIG_I2S_AK4642EN)
+//wjx __gpio_as_scc1();
+ __gpio_as_i2s_master(); //wjx
+#endif
+#if defined(CONFIG_I2S_TSC2301) || defined(CONFIG_I2S_TLC320AIC23)
+ __gpio_as_ssi();
+#endif
+ //__gpio_as_ac97();
+#if defined(CONFIG_I2S_TSC2301) || defined(CONFIG_I2S_TLC320AIC23) || defined(CONFIG_I2S_CS42L51)
+ __gpio_as_i2s_slave();
+#endif
+//wjx __gpio_as_cim();
+ __gpio_as_msc();
+
+/* wjx
+ __gpio_as_output(GPIO_LED_EN);
+ __gpio_set_pin(GPIO_LED_EN);
+
+ __gpio_as_output(GPIO_DISP_OFF_N);
+ __gpio_set_pin(GPIO_DISP_OFF_N);
+*/
+ __gpio_as_output(GPIO_PWM0);
+ __gpio_set_pin(GPIO_PWM0);
+
+
+//wjx __gpio_as_input(GPIO_RTC_IRQ);
+ __gpio_as_output(GPIO_USB_CLK_EN);
+ __gpio_set_pin(GPIO_USB_CLK_EN);

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boot-programs/jz4730.hhp Normal file
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boot-programs/thread0.ccp → boot-programs/keyboard.ccp
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boot-programs/lcd.ccp Normal file
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#pypp 0
// Iris: micro-kernel for a capability-based operating system.
// lcd.ccp: Display driver.
// Copyright 2009 Bas Wijnen <wijnen@debian.org>
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
#include "iris.h"
// gpio stuff
#define D(n) (*(volatile unsigned *)(0x00 + 0x30 * n + gpio_address))
#define DI(n) (*(volatile unsigned *)(0x04 + 0x30 * n + gpio_address))
#define PU(n) (*(volatile unsigned *)(0x0c + 0x30 * n + gpio_address))
#define AL(n) (*(volatile unsigned *)(0x10 + 0x30 * n + gpio_address))
#define AU(n) (*(volatile unsigned *)(0x14 + 0x30 * n + gpio_address))
#define IE(n) (*(volatile unsigned *)(0x20 + 0x30 * n + gpio_address))
// pwm stuff
#define CTR (*(volatile unsigned char *)(pwm_address + 0x00))
#define PER (*(volatile unsigned short *)(pwm_address + 0x04))
#define DUT (*(volatile unsigned short *)(pwm_address + 0x08))
#define CPM_MSCR (*(volatile unsigned *)(cpm_address + 0x20))
// Mapping address for I/O memory.
unsigned const gpio_address = 0x00001000
unsigned const pwm_address = 0x00002000
unsigned const lcd_address = 0x00003000
unsigned const cpm_address = 0x00004000
//#define PWM0_BASE 0xB0050000
//#define PWM1_BASE 0xB0051000
/* PWM Control Register (PWM_CTR) */
//#define PWM_CTR_EN (1 << 7)
//#define PWM_CTR_SD (1 << 6)
//#define PWM_CTR_PRESCALE_MASK 0x3f
/* PWM Period Register (PWM_PER) */
//#define PWM_PER_PERIOD_MASK 0x3ff
/* PWM Duty Register (PWM_DUT) */
//#define PWM_DUT_FDUTY (1 << 10)
//#define PWM_DUT_DUTY_MASK 0x3ff
// Pin definitions, all in port 2.
#define PWM_ENABLE (1 << 30)
#define SPEN (1 << 0) //LCD_SPL
#define SPCK (1 << 1) //LCD_CLS
#define SPDA (1 << 2) //LCD_PS
#define LCD_RET (1 << 3) //LCD_REV //use for lcd reset
// Lcd register definitions.
#define LCD_CFG (*(volatile unsigned *)(lcd_address + 0x00))
#define LCD_VSYNC (*(volatile unsigned *)(lcd_address + 0x04))
#define LCD_HSYNC (*(volatile unsigned *)(lcd_address + 0x08))
#define LCD_VAT (*(volatile unsigned *)(lcd_address + 0x0c))
#define LCD_DAH (*(volatile unsigned *)(lcd_address + 0x10))
#define LCD_DAV (*(volatile unsigned *)(lcd_address + 0x14))
#define LCD_PS (*(volatile unsigned *)(lcd_address + 0x18))
#define LCD_CLS (*(volatile unsigned *)(lcd_address + 0x1c))
#define LCD_SPL (*(volatile unsigned *)(lcd_address + 0x20))
#define LCD_REV (*(volatile unsigned *)(lcd_address + 0x24))
#define LCD_CTRL (*(volatile unsigned *)(lcd_address + 0x30))
#define LCD_STATE (*(volatile unsigned *)(lcd_address + 0x34))
#define LCD_IID (*(volatile unsigned *)(lcd_address + 0x38))
#define LCD_DA0 (*(volatile unsigned *)(lcd_address + 0x40))
#define LCD_SA0 (*(volatile unsigned *)(lcd_address + 0x44))
#define LCD_FID0 (*(volatile unsigned *)(lcd_address + 0x48))
#define LCD_CMD0 (*(volatile unsigned *)(lcd_address + 0x4c))
#define LCD_DA1 (*(volatile unsigned *)(lcd_address + 0x50))
#define LCD_SA1 (*(volatile unsigned *)(lcd_address + 0x54))
#define LCD_FID1 (*(volatile unsigned *)(lcd_address + 0x58))
#define LCD_CMD1 (*(volatile unsigned *)(lcd_address + 0x5c))
// Bit definitions.
#define LCD_CFG_PDW_BIT 4
#define LCD_CFG_PDW_MASK (0x03 << LCD_DEV_PDW_BIT)
#define LCD_CFG_PDW_1 (0 << LCD_DEV_PDW_BIT)
#define LCD_CFG_PDW_2 (1 << LCD_DEV_PDW_BIT)
#define LCD_CFG_PDW_4 (2 << LCD_DEV_PDW_BIT)
#define LCD_CFG_PDW_8 (3 << LCD_DEV_PDW_BIT)
#define LCD_CFG_MODE_BIT 0
#define LCD_CFG_MODE_MASK (0x0f << LCD_DEV_MODE_BIT)
#define LCD_CFG_MODE_GENERIC_TFT (0 << LCD_DEV_MODE_BIT)
#define LCD_CFG_MODE_SHARP_HR (1 << LCD_DEV_MODE_BIT)
#define LCD_CFG_MODE_CASIO_TFT (2 << LCD_DEV_MODE_BIT)
#define LCD_CFG_MODE_SAMSUNG_ALPHA (3 << LCD_DEV_MODE_BIT)
#define LCD_CFG_MODE_NONINTER_CCIR656 (4 << LCD_DEV_MODE_BIT)
#define LCD_CFG_MODE_INTER_CCIR656 (5 << LCD_DEV_MODE_BIT)
#define LCD_CFG_MODE_SINGLE_CSTN (8 << LCD_DEV_MODE_BIT)
#define LCD_CFG_MODE_SINGLE_MSTN (9 << LCD_DEV_MODE_BIT)
#define LCD_CFG_MODE_DUAL_CSTN (10 << LCD_DEV_MODE_BIT)
#define LCD_CFG_MODE_DUAL_MSTN (11 << LCD_DEV_MODE_BIT)
#define LCD_VSYNC_VPS_BIT 16
#define LCD_VSYNC_VPS_MASK (0xffff << LCD_VSYNC_VPS_BIT)
#define LCD_VSYNC_VPE_BIT 0
#define LCD_VSYNC_VPE_MASK (0xffff << LCD_VSYNC_VPS_BIT)
#define LCD_HSYNC_HPS_BIT 16
#define LCD_HSYNC_HPS_MASK (0xffff << LCD_HSYNC_HPS_BIT)
#define LCD_HSYNC_HPE_BIT 0
#define LCD_HSYNC_HPE_MASK (0xffff << LCD_HSYNC_HPE_BIT)
#define LCD_VAT_HT_BIT 16
#define LCD_VAT_HT_MASK (0xffff << LCD_VAT_HT_BIT)
#define LCD_VAT_VT_BIT 0
#define LCD_VAT_VT_MASK (0xffff << LCD_VAT_VT_BIT)
#define LCD_DAH_HDS_BIT 16
#define LCD_DAH_HDS_MASK (0xffff << LCD_DAH_HDS_BIT)
#define LCD_DAH_HDE_BIT 0
#define LCD_DAH_HDE_MASK (0xffff << LCD_DAH_HDE_BIT)
#define LCD_DAV_VDS_BIT 16
#define LCD_DAV_VDS_MASK (0xffff << LCD_DAV_VDS_BIT)
#define LCD_DAV_VDE_BIT 0
#define LCD_DAV_VDE_MASK (0xffff << LCD_DAV_VDE_BIT)
#define LCD_CTRL_BST_BIT 28
#define LCD_CTRL_BST_MASK (0x03 << LCD_CTRL_BST_BIT)
#define LCD_CTRL_BST_4 (0 << LCD_CTRL_BST_BIT)
#define LCD_CTRL_BST_8 (1 << LCD_CTRL_BST_BIT)
#define LCD_CTRL_BST_16 (2 << LCD_CTRL_BST_BIT)
#define LCD_CTRL_RGB555 (1 << 27)
#define LCD_CTRL_OFUP (1 << 26)
#define LCD_CTRL_FRC_BIT 24
#define LCD_CTRL_FRC_MASK (0x03 << LCD_CTRL_FRC_BIT)
#define LCD_CTRL_FRC_16 (0 << LCD_CTRL_FRC_BIT)
#define LCD_CTRL_FRC_4 (1 << LCD_CTRL_FRC_BIT)
#define LCD_CTRL_FRC_2 (2 << LCD_CTRL_FRC_BIT)
#define LCD_CTRL_PDD_BIT 16
#define LCD_CTRL_PDD_MASK (0xff << LCD_CTRL_PDD_BIT)
#define LCD_CTRL_EOFM (1 << 13)
#define LCD_CTRL_SOFM (1 << 12)
#define LCD_CTRL_OFUM (1 << 11)
#define LCD_CTRL_IFUM0 (1 << 10)
#define LCD_CTRL_IFUM1 (1 << 9)
#define LCD_CTRL_LDDM (1 << 8)
#define LCD_CTRL_QDM (1 << 7)
#define LCD_CTRL_BEDN (1 << 6)
#define LCD_CTRL_PEDN (1 << 5)
#define LCD_CTRL_DIS (1 << 4)
#define LCD_CTRL_ENA (1 << 3)
#define LCD_CTRL_BPP_BIT 0
#define LCD_CTRL_BPP_MASK (0x07 << LCD_CTRL_BPP_BIT)
#define LCD_CTRL_BPP_1 (0 << LCD_CTRL_BPP_BIT)
#define LCD_CTRL_BPP_2 (1 << LCD_CTRL_BPP_BIT)
#define LCD_CTRL_BPP_4 (2 << LCD_CTRL_BPP_BIT)
#define LCD_CTRL_BPP_8 (3 << LCD_CTRL_BPP_BIT)
#define LCD_CTRL_BPP_16 (4 << LCD_CTRL_BPP_BIT)
#define LCD_STATE_QD (1 << 7)
#define LCD_STATE_EOF (1 << 5)
#define LCD_STATE_SOF (1 << 4)
#define LCD_STATE_OFU (1 << 3)
#define LCD_STATE_IFU0 (1 << 2)
#define LCD_STATE_IFU1 (1 << 1)
#define LCD_STATE_LDD (1 << 0)
#define LCD_CMD_SOFINT (1 << 31)
#define LCD_CMD_EOFINT (1 << 30)
#define LCD_CMD_PAL (1 << 28)
#define LCD_CMD_LEN_BIT 0
#define LCD_CMD_LEN_MASK (0xffffff << LCD_CMD_LEN_BIT)
static void udelay (unsigned us):
for unsigned i = 0; i < us; ++i:
for unsigned k = 0; k < 100; ++k:
IE (2) &= ~SPEN
static void mdelay (unsigned ms):
udelay (1000 * ms)
static unsigned int get_pllout ():
unsigned plcr = CPM_PLCR1
if (plcr & CPM_PLCR1_PLL1EN)
unsigned nf, nr, no
unsigned od[4] = {1, 2, 2, 4}
nf = (plcr & CPM_PLCR1_PLL1FD_MASK) >> CPM_PLCR1_PLL1FD_BIT
nr = (plcr & CPM_PLCR1_PLL1RD_MASK) >> CPM_PLCR1_PLL1RD_BIT
no = od[((plcr & CPM_PLCR1_PLL1OD_MASK) >> CPM_PLCR1_PLL1OD_BIT)]
return (JZ_EXTAL) / ((nr+2) * no) * (nf+2)
else
return JZ_EXTAL
// level is in the range [0, 300]
static void set_backlight (unsigned level):
DUT = level
if level:
CTR = 0xbf
D (2) |= PWM_ENABLE
else:
CTR = 0x3f
D (2) &= ~PWM_ENABLE
// Write to a register. Value must be in range [0, 0xff].
static void write_reg (unsigned reg, unsigned value):
unsigned data = (reg << 0xa) | 0x200 | value
D (2) |= SPEN
D (2) = (D (2) & ~SPDA) | SPCK
D (2) &= ~SPEN
udelay(25)
for unsigned i = 0; i < 16; ++i:
D (2) &= ~SPCK
if data & 0x8000:
D (2) |= SPDA
else:
D (2) &= ~SPDA
udelay (25)
D (2) |= SPCK
udelay (25)
data <<= 1
D (2) |= SPEN
udelay(200)
static void lcd_enable ():
udelay (50)
D (2) &= ~LCD_RET
mdelay(150)
D (2) |= LCD_RET
mdelay(10)
// These values have been copied from the linux source.
// I have no idea what they do.
write_reg (0x00, 0x03)
write_reg (0x01, 0x40)
write_reg (0x02, 0x11)
write_reg (0x03, 0xcd)
write_reg (0x04, 0x32)
write_reg (0x05, 0x0e)
write_reg (0x07, 0x03)
write_reg (0x08, 0x08)
write_reg (0x09, 0x32)
write_reg (0x0A, 0x88)
write_reg (0x0B, 0xc6)
write_reg (0x0C, 0x20)
write_reg (0x0D, 0x20)
set_backlight (300)
static void lcd_disable ():
write_reg (0x00, 0x03)
set_backlight (0)
static void reset ():
// Use gpio pins as pwm.
AUR (2) = (AUR (2) & ~0x0fffffff) | 0x50000000
// Use gpio pins as lcd master.
ALR (1) = (ALR (1) & ~0x0000ffff) | 0x55550000
AUR (1) = 0x556a5555
// initialize things.
IE(2) &= ~(PWM_ENABLE | LCD_RET | SPEN | SPCK | SPDA)
DI(2) |= PWM_ENABLE | LCD_RET | SPEN | SPCK | SPDA
udelay (50)
D (2) &= ~LCD_RET
mdelay (150)
D (2) |= LCD_RET
mdelay (10)
lcd_enable ()
// For now, support only 16 bpp.
// Screen is 800x480 tft.
LCD_CTRL = LCD_CTRL_BPP_16 | LCD_CTRL_BST_16
LCD_VSYNC = 20
LCD_HSYNC = 80
LCD_DAV = (20 << 16) | 500
LCD_DAH = (80 << 16) | 880
LCD_VAT = (880 << 16) | 500
LCD_CFG = MODE_TFT_GEN | PCLK_N | VSYNC_N
// Stop lcd.
CPM_MSCR |= 1 << 7
unsigned pclk = 60 * (800 * 3 + 80) * 500
unsigned pllout = get_pllout ()
CPM_CFCR2 = pllout / pclk - 1
unsigned v = pllout / (pclk * 4) - 1
while v < 0xf && pllout / (v + 1) > 150000000:
++v
CPM_CFCR = (CPM_CFCR & ~CPM_CFCR_LFR_MASK) | (v << CPM_CFCR_LFR_BIT) | CPM_CFCR_UPE
// Start lcd.
CPM_MSCR &= ~(1 << 7)
mdelay (1)
static void map_io (unsigned physical, unsigned address):
Capability page = memory_create_page (__my_memory)
alloc_physical (page, physical, 0)
memory_map (__my_memory, page, address, 1)
//drop (page)
int main ():
map_io (0x10010000, gpio_address)
map_io (0x10050000, pwm_address)
map_io (0x13050000, lcd_address)
map_io (0x10000000, cpm_address)
reset ()
while true:
Message msg
if !wait (&msg):
continue
switch msg.protected_data:
case LCD_BACKLIGHT:
set_backlight (c.data[0] > 300 ? 300 : c.data[0])
break
case LCD_RESET:
reset ()
break

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boot-programs/thread1.ccp
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@@ -1,23 +0,0 @@
#pypp 0
// Iris: micro-kernel for a capability-based operating system.
// thread1.ccp: Testing userspace thread.
// Copyright 2009 Bas Wijnen <wijnen@debian.org>
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
#include "iris.h"
int main ():
while true:
schedule ()