mirror of
git://projects.qi-hardware.com/iris.git
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reorganize headers
This commit is contained in:
Bas Wijnen
parent
40a9a29c2d
commit
1c1c256f79
@ -16,9 +16,9 @@
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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#include <iris.h>
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#include "devices.hh"
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#include "jz4730.hh"
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#define ARCH
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#include "arch.hh"
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// GPIO pins for the keyboard: (port.pin)
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// Cols = 3.0, 3.1, 3.2, 3.3, 3.4, 3.5, 3.6, 3.7, 3.8, 3.9, 3.10, 3.11, 3.12, 3.13, 3.14, 3.15, 3.29
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@ -16,9 +16,9 @@
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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#include <iris.h>
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#include "jz4730.hh"
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#include "devices.hh"
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#define ARCH
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#include "arch.hh"
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// Pin definitions, all in port 2.
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#define PWM_ENABLE (1 << 30)
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@ -35,7 +35,7 @@ uimage:
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mips/entry.o: $(boot_threads)
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mips/init.o: TARGET_FLAGS = -I/usr/include
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$(boot_threads): TARGET_FLAGS = -I.
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$(boot_threads): boot-programs/jz4730.hh boot-programs/devices.hh
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$(boot_threads): mips/jz4730.hh boot-programs/devices.hh
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# Transform ':' into ';' so vim doesn't think there are errors.
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uimage: kernel.raw.gz Makefile mips/Makefile.arch
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@ -20,6 +20,11 @@
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#define _ARCH_HH
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#ifdef ARCH
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#ifndef ASM
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#include "jz4730.hh"
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#endif
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#define reg_hack(x...) #x
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#define cp0_get(reg, target) do { __asm__ volatile ("mfc0 %0, $" reg_hack(reg) : "=r" (target)); } while (0)
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#define cp0_set(reg, value) do { __asm__ volatile ("mtc0 %0, $" reg_hack(reg) :: "r" (value)); } while (0)
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@ -59,8 +64,10 @@
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#define CP0_DATA_HI 29, 1
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#define CP0_ERROR_EPC 30
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#define CP0_DESAVE 31
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#endif
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#ifdef __KERNEL
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// register save positions in Thread
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#define SAVE_PC (5 * 4)
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#define SAVE_SP (SAVE_PC + 4)
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@ -157,6 +164,8 @@ extern unsigned thread_start[NUM_THREADS + 1]
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// Fast pointer to page directory, for tlb miss events
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extern unsigned **directory
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#endif // defined ASM
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#endif // not defined ASM
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#endif // defined __KERNEL
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#endif
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@ -25,6 +25,7 @@
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#define ARCH
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#define ASM
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#define __KERNEL
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#include "arch.hh"
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addr_000:
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@ -2,44 +2,8 @@
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#ifndef __JZ4730_HH__
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#define __JZ4730_HH__
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#include <iris.h>
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#define JZ_EXTAL 3686400
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// Base addresses are the place where the pages are mapped.
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#define HARB_BASE 0x00000000
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#define EMC_BASE 0x00001000
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#define DMAC_BASE 0x00002000
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#define UHC_BASE 0x00003000
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#define UDC_BASE 0x00004000
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#define LCD_BASE 0x00005000
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#define CIM_BASE 0x00006000
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#define ETH_BASE 0x00007000
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#define NBM_BASE 0x00008000
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#define CPM_BASE 0x00009000
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#define INTC_BASE 0x0000a000
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#define OST_BASE 0x0000b000
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#define RTC_BASE 0x0000c000
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#define WDT_BASE 0x0000d000
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#define GPIO_BASE 0x0000e000
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#define AIC_BASE 0x0000f000
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#define MSC_BASE 0x00010000
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#define UART0_BASE 0x00011000
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#define UART1_BASE 0x00012000
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#define UART2_BASE 0x00013000
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#define UART3_BASE 0x00014000
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#define FIR_BASE 0x00015000
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#define SCC_BASE 0x00016000
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#define SCC0_BASE 0x00017000
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#define I2C_BASE 0x00018000
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#define SSI_BASE 0x00019000
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#define SCC1_BASE 0x0001a000
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#define PWM0_BASE 0x0001b000
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#define PWM1_BASE 0x0001c000
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#define DES_BASE 0x0001d000
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#define UPRT_BASE 0x0001e000
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#define KBC_BASE 0x0001f000
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// Physical addresses are where they really are.
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// (In kernel space you need to add 0xa0000000 to see them unmapped uncached in kseg2.)
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#define HARB_PHYSICAL 0x13000000
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@ -75,6 +39,76 @@
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#define UPRT_PHYSICAL 0x10061000
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#define KBC_PHYSICAL 0x10062000
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#ifdef __KERNEL
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#define HARB_BASE (HARB_PHYSICAL + 0xa0000000)
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#define EMC_BASE (EMC_PHYSICAL + 0xa0000000)
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#define DMAC_BASE (DMAC_PHYSICAL + 0xa0000000)
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#define UHC_BASE (UHC_PHYSICAL + 0xa0000000)
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#define UDC_BASE (UDC_PHYSICAL + 0xa0000000)
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#define LCD_BASE (LCD_PHYSICAL + 0xa0000000)
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#define CIM_BASE (CIM_PHYSICAL + 0xa0000000)
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#define ETH_BASE (ETH_PHYSICAL + 0xa0000000)
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#define NBM_BASE (NBM_PHYSICAL + 0xa0000000)
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#define CPM_BASE (CPM_PHYSICAL + 0xa0000000)
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#define INTC_BASE (INTC_PHYSICAL + 0xa0000000)
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#define OST_BASE (OST_PHYSICAL + 0xa0000000)
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#define RTC_BASE (RTC_PHYSICAL + 0xa0000000)
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#define WDT_BASE (WDT_PHYSICAL + 0xa0000000)
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#define GPIO_BASE (GPIO_PHYSICAL + 0xa0000000)
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#define AIC_BASE (AIC_PHYSICAL + 0xa0000000)
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#define MSC_BASE (MSC_PHYSICAL + 0xa0000000)
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#define UART0_BASE (UART0_PHYSICAL + 0xa0000000)
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#define UART1_BASE (UART1_PHYSICAL + 0xa0000000)
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#define UART2_BASE (UART2_PHYSICAL + 0xa0000000)
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#define UART3_BASE (UART3_PHYSICAL + 0xa0000000)
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#define FIR_BASE (FIR_PHYSICAL + 0xa0000000)
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#define SCC_BASE (SCC_PHYSICAL + 0xa0000000)
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#define SCC0_BASE (SCC0_PHYSICAL + 0xa0000000)
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#define I2C_BASE (I2C_PHYSICAL + 0xa0000000)
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#define SSI_BASE (SSI_PHYSICAL + 0xa0000000)
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#define SCC1_BASE (SCC1_PHYSICAL + 0xa0000000)
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#define PWM0_BASE (PWM0_PHYSICAL + 0xa0000000)
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#define PWM1_BASE (PWM1_PHYSICAL + 0xa0000000)
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#define DES_BASE (DES_PHYSICAL + 0xa0000000)
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#define UPRT_BASE (UPRT_PHYSICAL + 0xa0000000)
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#define KBC_BASE (KBC_PHYSICAL + 0xa0000000)
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#else
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#include <iris.h>
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// Base addresses are the place where the pages are mapped.
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#define HARB_BASE 0x00000000
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#define EMC_BASE 0x00001000
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#define DMAC_BASE 0x00002000
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#define UHC_BASE 0x00003000
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#define UDC_BASE 0x00004000
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#define LCD_BASE 0x00005000
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#define CIM_BASE 0x00006000
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#define ETH_BASE 0x00007000
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#define NBM_BASE 0x00008000
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#define CPM_BASE 0x00009000
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#define INTC_BASE 0x0000a000
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#define OST_BASE 0x0000b000
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#define RTC_BASE 0x0000c000
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#define WDT_BASE 0x0000d000
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#define GPIO_BASE 0x0000e000
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#define AIC_BASE 0x0000f000
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#define MSC_BASE 0x00010000
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#define UART0_BASE 0x00011000
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#define UART1_BASE 0x00012000
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#define UART2_BASE 0x00013000
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#define UART3_BASE 0x00014000
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#define FIR_BASE 0x00015000
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#define SCC_BASE 0x00016000
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#define SCC0_BASE 0x00017000
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#define I2C_BASE 0x00018000
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#define SSI_BASE 0x00019000
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#define SCC1_BASE 0x0001a000
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#define PWM0_BASE 0x0001b000
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#define PWM1_BASE 0x0001c000
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#define DES_BASE 0x0001d000
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#define UPRT_BASE 0x0001e000
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#define KBC_BASE 0x0001f000
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// Map IO memory (requires a priviledged __my_thread capability).
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static void __map_io (unsigned physical, unsigned mapping):
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Capability page = memory_create_page (__my_memory)
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@ -83,6 +117,7 @@ static void __map_io (unsigned physical, unsigned mapping):
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// 1 means writable.
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memory_map (__my_memory, page, mapping, 1)
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//drop (page)
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#endif
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// Physical addresses are where they really are.
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#define map_harb() do { __map_io (HARB_PHYSICAL, HARB_BASE); } while (0)
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