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make udc work

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This commit is contained in:
Bas Wijnen
2009-09-29 23:48:33 +02:00
parent 20d15f0745
commit 431b38acb9
11 changed files with 139 additions and 90 deletions
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4
mips/nanonote/board.ccp
View File

@@ -33,9 +33,9 @@ void board_init ():
gpio_as_gpio (3, 0x05fc0000)
tcu_stop_counter (0)
tcu_select_extalclk (0)
tcu_select_clk_div1 (0)
tcu_select_clk_div4 (0)
tcu_disable_pwm_output (0)
tcu_set_full_data (0, JZ_EXTAL / HZ)
tcu_set_full_data (0, JZ_EXTAL / HZ / 4)
tcu_mask_half_match_irq (0)
tcu_clear_full_match_flag (0)
tcu_unmask_full_match_irq (0)

23
mips/nanonote/jz4740.hhp
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@@ -22,7 +22,7 @@
#define __JZ4740_HH__
// Main clock, for cpu, serial port, and with divisors for most other hardware
#define JZ_EXTAL 3686400 /* 3.6864 MHz */
#define JZ_EXTAL 12000000 /* 3.6864 MHz */
// RTC clock
#define RTC_CLOCK 32768 /* 32.768 KHz */
// Interrupt source used for system timer
@@ -1883,17 +1883,16 @@ void cdelay (unsigned cs):
#define UDC_TESTMODE REG8 (UDC_BASE + 0x0f) // USB test mode 8-bit
#define UDC_CSR0 REG8 (UDC_BASE + 0x12) // EP0 CSR 8-bit
#define UDC_INMAXP REG16 (UDC_BASE + 0x10) // EP1-2 IN Max Pkt Size 16-bit
#define UDC_INCSR REG16 (UDC_BASE + 0x12) // EP1-2 IN CSR LSB 8/16bit
#define UDC_INCSRH REG8 (UDC_BASE + 0x13) // EP1-2 IN CSR MSB 8-bit
#define UDC_OUTMAXP REG16 (UDC_BASE + 0x14) // EP1 OUT Max Pkt Size 16-bit
#define UDC_OUTCSR REG16 (UDC_BASE + 0x16) // EP1 OUT CSR LSB 8/16bit
#define UDC_OUTCSRH REG8 (UDC_BASE + 0x17) // EP1 OUT CSR MSB 8-bit
#define UDC_OUTCOUNT REG16 (UDC_BASE + 0x18) // bytes in EP0/1 OUT FIFO 16-bit
#define UDC_INMAXP(ep) REG16 (UDC_BASE + 0x100 + 0x10 * (ep) + 0x10) // EP1-2 IN Max Pkt Size 16-bit
#define UDC_INCSR(ep) REG16 (UDC_BASE + 0x100 + 0x10 * (ep) + 0x12) // EP1-2 IN CSR LSB 8/16bit
#define UDC_INCSRH(ep) REG8 (UDC_BASE + 0x100 + 0x10 * (ep) + 0x13) // EP1-2 IN CSR MSB 8-bit
#define UDC_OUTMAXP(ep) REG16 (UDC_BASE + 0x100 + 0x10 * (ep) + 0x14) // EP1 OUT Max Pkt Size 16-bit
#define UDC_OUTCSR(ep) REG16 (UDC_BASE + 0x100 + 0x10 * (ep) + 0x16) // EP1 OUT CSR LSB 8/16bit
#define UDC_OUTCSRH(ep) REG8 (UDC_BASE + 0x100 + 0x10 * (ep) + 0x17) // EP1 OUT CSR MSB 8-bit
#define UDC_OUTCOUNT(ep) REG16 (UDC_BASE + 0x100 + 0x10 * (ep) + 0x18) // bytes in EP0/1 OUT FIFO 16-bit
#define UDC_FIFO_EP0 REG32 (UDC_BASE + 0x20)
#define UDC_FIFO_EP1 REG32 (UDC_BASE + 0x24)
#define UDC_FIFO_EP2 REG32 (UDC_BASE + 0x28)
#define UDC_FIFO(ep) REG32 (UDC_BASE + 0x20 + 4 * (ep))
#define UDC_FIFO8(ep) REG8 (UDC_BASE + 0x20 + 4 * (ep))
#define UDC_EPINFO REG32 (UDC_BASE + 0x78) // Endpoint information
#define UDC_RAMINFO REG32 (UDC_BASE + 0x79) // RAM information
@@ -2354,7 +2353,7 @@ static void pll_init ():
cfcr = CPM_CPCCR_CLKOEN | (n2FR[1] << CPM_CPCCR_CDIV_BIT) | (n2FR[PHM_DIV] << CPM_CPCCR_HDIV_BIT) | (n2FR[PHM_DIV] << CPM_CPCCR_PDIV_BIT) | (n2FR[PHM_DIV] << CPM_CPCCR_MDIV_BIT) | (n2FR[PHM_DIV] << CPM_CPCCR_LDIV_BIT)
pllout2 = (cfcr & CPM_CPCCR_PCS) ? 252000000 : (252000000 / 2)
CPM_UHCCDR = pllout2 / 48000000 - 1
nf = 252000000 * 2 / 12000000
nf = 252000000 * 2 / JZ_EXTAL
plcr1 = ((nf - 2) << CPM_CPPCR_PLLM_BIT) | (0 << CPM_CPPCR_PLLN_BIT) | (0 << CPM_CPPCR_PLLOD_BIT) | (0x20 << CPM_CPPCR_PLLST_BIT) | CPM_CPPCR_PLLEN
CPM_CPCCR = cfcr
CPM_CPPCR = plcr1

7
mips/nanonote/nanonote-boot.ccp
View File

@@ -21,6 +21,7 @@
#include <fstream>
#include <sstream>
#include <iostream>
#include <iomanip>
asm volatile (".section .rodata\n"
".globl stage1\n"
@@ -165,8 +166,12 @@ void nanonote::boot (std::string const &data, unsigned load, unsigned start):
send_file (load, data.size (), data.data ())
request (VR_FLUSH_CACHES)
request (VR_PROGRAM_START2, start)
sleep (1)
get_cpu_info ()
std::cerr << "info: " << cpu_info << std::endl
std::cerr << "info: ";
for unsigned i = 0; i < cpu_info.size (); ++i:
std::cerr << std::setfill ('0') << std::setw (2) << std::hex << (cpu_info[i] & 0xff);
std::cerr << std::endl
int main (int argc, char **argv):
if argc != 3: