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Code

working lcd driver

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This commit is contained in:
Bas Wijnen 2009-12-18 09:00:38 +01:00
parent cf496f031f
commit 85948735ab
10 changed files with 65 additions and 44 deletions
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3
boot-programs/buzzer.ccp
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@ -28,8 +28,7 @@ class DevBuzzer:
DevBuzzer ():
is_beeping = false
tcu_stop_counter (pwm)
//tcu_select_extalclk (pwm)
tcu_select_pclk (pwm)
tcu_select_extalclk (pwm)
tcu_select_clk_div64 (pwm)
tcu_enable_pwm_output (pwm)
void stop ():

38
boot-programs/lcd.ccp
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@ -121,7 +121,7 @@ static void reset ():
#elif defined (NANONOTE)
// Note that the sync pulse is part of the pre-display region.
// Horizontal timings.
unsigned hsync = 1, hpre = 141, hpost = 273
unsigned hsync = 1, hpre = 70, hpost = 273
// Vertical timings.
unsigned vsync = 1, vpre = 21, vpost = 2
// 3 clocks per pixel.
@ -129,7 +129,7 @@ static void reset ():
// Bits per pixel.
unsigned bpp = LCD_CTRL_BPP_18_24
// Configuration.
unsigned cfg = LCD_CFG_MODE_SERIAL_TFT | LCD_CFG_HSP | LCD_CFG_VSP
unsigned cfg = LCD_CFG_MODE_SERIAL_TFT | LCD_CFG_HSP | LCD_CFG_VSP | LCD_CFG_PCP
// Set up SPI pins.
gpio_as_output (SP_PORT, (1 << SPEN) | (1 << SPCK) | (1 << SPDA))
gpio_set (SP_PORT, (1 << SPEN) | (1 << SPCK))
@ -139,7 +139,7 @@ static void reset ():
// Note that the sync pulse is part of the pre-display region.
unsigned vpe = vsync, vds = vpre, vde = vds + v, vt = vde + vpost
unsigned hpe = hsync, hds = hpre, hde = hds + cpp * h, ht = hde + hpost
unsigned hpe = hsync, hds = hpre, hde = hds + h, ht = hde + hpost
cpm_stop_lcd ()
@ -156,17 +156,11 @@ static void reset ():
CPM_CFCR |= CPM_CFCR_UPE
#elif defined (NANONOTE)
unsigned val = cpm_get_pllout2 () / pixclock - 1
kdebug ("clock: ")
kdebug_num (val)
kdebug ("\n")
//assert (val < 0x400)
//cpm_set_pixdiv (val)
//cpm_set_pixdiv (12)
val = cpm_get_pllout2 () / (pixclock * 3) - 1
kdebug ("clock: ")
kdebug_num (val)
kdebug ("\n")
assert (val < 0x20)
//cpm_set_ldiv (val)
// Update dividers.
@ -179,7 +173,7 @@ static void reset ():
#ifdef NANONOTE
// Reset the controller.
//write_reg (BACKLIGHT1, 0x1e)
write_reg (BACKLIGHT1, 0x1e)
// Enable display.
write_reg (BACKLIGHT1, 0x5f)
// Set data to rgbrgbrgb input, with a delta color filter.
@ -252,6 +246,15 @@ enum captype:
#endif
SET_EOF_CB
static unsigned spot (unsigned x, unsigned y, unsigned cx, unsigned cy):
unsigned dx2 = (x - cx) * (x - cx)
unsigned dy2 = (y - cy) * (y - cy)
unsigned d2 = dx2 + dy2
unsigned l = 120
if d2 >= l * l:
return 0
return ((l * l - d2 - 1) << 8) / (l * l)
Kernel::Num start ():
map_lcd ()
map_cpm ()
@ -265,21 +268,18 @@ Kernel::Num start ():
assert (physical & PAGE_MASK && ~physical)
for unsigned i = 0; i < pages; ++i:
Kernel::Page p = Kernel::my_memory.create_page ()
p.alloc_physical (physical + i * PAGE_SIZE, false, true)
Kernel::my_memory.map (p, (unsigned)LCD_FRAMEBUFFER_BASE + i * PAGE_SIZE)
p.alloc_physical (physical + (i << PAGE_BITS), false, true)
Kernel::my_memory.map (p, (unsigned)LCD_FRAMEBUFFER_BASE + (i << PAGE_BITS))
Kernel::free_cap (p)
for unsigned y = 0; y < v; ++y:
unsigned g = (y << 8) / v
for unsigned x = 0; x < h; ++x:
unsigned r = (x << 8) / h
unsigned b = ((x + y) << 8) / (h + v)
unsigned r = spot (x, y, 100, 160)
unsigned g = spot (x, y, 160, 60)
unsigned b = spot (x, y, 220, 160)
#if defined (TRENDTAC)
LCD_FRAMEBUFFER_BASE[y * h + x] = ((r >> 3) << 11) | ((g >> 2) << 5) | (b >> 3)
#elif defined (NANONOTE)
LCD_FRAMEBUFFER_BASE[(y * h + x) * Bpp + 3] = 0
LCD_FRAMEBUFFER_BASE[(y * h + x) * Bpp + 2] = r
LCD_FRAMEBUFFER_BASE[(y * h + x) * Bpp + 1] = g
LCD_FRAMEBUFFER_BASE[(y * h + x) * Bpp + 0] = b
LCD_FRAMEBUFFER_BASE[y * h + x] = (r << 16) | (g << 8) | b
#else
#error "Define your framebuffer format."
#endif

1
invoke.ccp
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@ -739,7 +739,6 @@ static void caps_invoke (unsigned cmd, unsigned target, Kernel::Num protected_da
if c->data[1].l >= caps->size:
dpanic (0, "invalid caps for print")
return
dbg_code.h = (unsigned)caps->cap (c->data[1].l)
kCapRef cap (caps, c->data[1].l)
kCapRef orig (caps, c->data[1].l)
while cap->parent.valid ():

2
iris.hhp
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@ -487,7 +487,7 @@ namespace Kernel:
my_thread.call (CAP_MASTER_DIRECT | Thread::DBG_SEND, Num (code, bits))
inline void reboot ():
my_thread.call (CAP_MASTER_DIRECT | Thread::PRIV_REBOOT)
inline void kernel_panic (unsigned code):
inline void panic (unsigned code):
my_thread.call (CAP_MASTER_DIRECT | Thread::PRIV_PANIC, code)
void Receiver::sleep (unsigned value):

21
memory.ccp
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@ -4,6 +4,7 @@
extern unsigned _end
static void clear_page (unsigned page, unsigned num = 1):
page = (page & ~0xc0000000) | 0xa0000000
for unsigned i = 0; i < (num << (PAGE_BITS - 2)); ++i:
((unsigned *)page)[i] = 0
if *((unsigned *)page) != 0 || ((unsigned *)page)[(num << (PAGE_BITS - 2)) - 1] != 0:
@ -51,6 +52,11 @@ unsigned init_memory (unsigned mem):
first_free->prev = NULL
first_free->next = NULL
first_free->num = ((mem & PAGE_MASK) - ((unsigned)first_free & ~0xc0000000)) >> PAGE_BITS
//dbg_log ("initial memory: ")
//dbg_log_num ((unsigned)first_free & ~0xc0000000)
//dbg_log ("+")
//dbg_log_num (first_free->num)
//dbg_log ("\n")
return first_free->num
unsigned phys_alloc (unsigned num):
@ -68,6 +74,11 @@ unsigned phys_alloc (unsigned num):
if p->next:
p->next->prev = p->prev
clear_page ((unsigned)p, num)
//dbg_log ("allocating ")
//dbg_log_num ((unsigned)p & ~0xc0000000)
//dbg_log ("+")
//dbg_log_num (num << PAGE_BITS)
//dbg_log ("\n")
return (unsigned)p
choice = p
if !choice:
@ -77,9 +88,19 @@ unsigned phys_alloc (unsigned num):
choice->num -= num
unsigned ret = (unsigned)choice + (choice->num << PAGE_BITS)
clear_page (ret, num)
//dbg_log ("allocating ")
//dbg_log_num (ret & ~0xc0000000)
//dbg_log ("+")
//dbg_log_num (num << PAGE_BITS)
//dbg_log ("\n")
return ret
void phys_free (unsigned page, unsigned num):
//dbg_log ("free ")
//dbg_log_num (page & ~0xc0000000)
//dbg_log ("+")
//dbg_log_num (num)
//dbg_log ("\n")
unsigned size = num << PAGE_BITS
if !first_free || (unsigned)first_free > page:
// This is the first free block.

6
mips/init.ccp
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@ -232,7 +232,8 @@ static void init_threads ():
// Initialize the kernel, finish by falling into the idle task.
void init (unsigned mem):
#ifndef NDEBUG
dbg_code = 0
// Initialize board-specific things.
board_init ()
#endif
must_wait = false
// Initialize kernel variables to empty.
@ -266,8 +267,7 @@ void init (unsigned mem):
for unsigned i = 0; i < 32; ++i:
arch_interrupt_receiver[i] = NULL
// Initialize board-specific things.
board_init ()
// Enable timer interrupts.
intc_unmask_irq (TIMER_INTERRUPT)
// Say we're handling an exception. Since we're going to enter the idle task, allow access to cp0.

1
mips/interrupts.ccp
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@ -251,6 +251,7 @@ kThread *exception ():
break
case 23:
// Reference to WatchHi/WatchLo address.
cp0_set0 (CP0_WATCH_LO)
current->raise (Kernel::ERR_WATCHPOINT, 0)
break
case 24:

24
mips/nanonote/board.ccp
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@ -21,28 +21,31 @@
#include "kernel.hh"
void board_init ():
unsigned cpm_uhccdr = CPM_UHCCDR
unsigned cpm_cpccr = CPM_CPCCR
unsigned cpm_cppcr = CPM_CPPCR
pll_init ()
cpm_stop_all ()
#ifndef NDEBUG
cpm_start_uart0 ()
cpm_start_tcu ()
cpm_start_lcd ()
gpio_as_uart0 ()
#endif
// Timer interrupts and buzzer.
cpm_start_tcu ()
// sdram memory.
gpio_as_sdram_16bit ()
// flash memory.
gpio_as_nand ()
// sound controller.
gpio_as_aic ()
// micro-sd controller.
gpio_as_msc ()
// display.
gpio_as_lcd_16bit ()
// buzzer.
gpio_as_pwm4 ()
// Set up memory.
setup_sdram ()
// Use some gpio pins for lcd.
gpio_as_gpio (2, (1 << 21) | (1 << 22) | (1 << 23))
gpio_as_gpio (3, 1 << 27)
gpio_as_output (2, (1 << 21) | (1 << 22) | (1 << 23))
gpio_as_output (3, 1 << 27)
// Set up keyboard: this breaks uart receive.
gpio_as_gpio (3, 0x05fc0000)
// Set up timed interrupts.
@ -55,6 +58,7 @@ void board_init ():
tcu_clear_full_match_flag (0)
tcu_unmask_full_match_irq (0)
tcu_start_counter (0)
#ifndef NDEBUG
// Set up uart.
UART0_IER = 0
UART0_FCR = 0
@ -68,12 +72,8 @@ void board_init ():
UART0_DLLR = uart_div
UART0_LCR = UARTLCR_WLEN_8 | UARTLCR_STOP1
UART0_FCR = UARTFCR_UUE | UARTFCR_FE | UARTFCR_RFLS | UARTFCR_TFLS
dbg_code.l = 1
dbg_log ("Serial port initialized\n")
dbg_log_num (CPM_CPCCR)
dbg_log ("+")
dbg_log_num (CPM_CPPCR)
dbg_log ("\n")
#endif
void arch_reboot ():
// Wait for serial port to be done.

11
mips/nanonote/jz4740.hhp
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@ -102,7 +102,7 @@
#define ETH_BASE 0x00014000
// Default lcd framebuffer mapping space.
#define LCD_FRAMEBUFFER_BASE ((unsigned char *)0x00015000)
#define LCD_FRAMEBUFFER_BASE ((unsigned *)0x00015000)
// Map IO memory (requires a priviledged Kernel::my_thread capability).
#include <iris.hh>
@ -2347,9 +2347,10 @@ static void gpio_disable_pull (unsigned p, unsigned pins):
//**************************************************************************
static void pll_init ():
// The cpu clock frequency
//unsigned const cpu_clock = 336000000
unsigned const cpu_clock = 210000000
unsigned const pixclock = 27000000
unsigned const cpu_clock = 336000000
//unsigned const cpu_clock = 200000000
//unsigned const pixclock = 13500000
unsigned const pixclock = 25846153
// Configure the pll frequency to cpu_clock.
CPM_CPPCR = ((cpu_clock * 2 / JZ_EXTAL - 2) << CPM_CPPCR_PLLM_BIT) | (0 << CPM_CPPCR_PLLN_BIT) | (0 << CPM_CPPCR_PLLOD_BIT) | (0x20 << CPM_CPPCR_PLLST_BIT) | CPM_CPPCR_PLLEN
// Set up dividers; see documentation for the meaning of all the values.
@ -3695,6 +3696,7 @@ static void setup_sdram ():
EMC_RTCSR = 0x83
EMC_RTCOR = 0x1f
#endif
#if 0
for unsigned i = 0; i < 5; ++i:
dbg_log ("memory: ")
dbg_log_num (EMC_SMCR (i), 8)
@ -3705,6 +3707,7 @@ static void setup_sdram ():
dbg_log (",")
dbg_log_num (EMC_RTCOR, 8)
dbg_log ("\n")
#endif
#endif
#endif

2
panic.ccp
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@ -21,8 +21,6 @@
#ifdef USE_SERIAL
void dbg_log_char (unsigned ch):
if dbg_code.l == 0:
return
while !(UART0_LSR & UARTLSR_TDRQ):
UART0_TDR = ch
#else