working lcd driver

mips/init.ccp

@@ -232,7 +232,8 @@ static void init_threads ():
 // Initialize the kernel, finish by falling into the idle task.
 void init (unsigned mem):
 	#ifndef NDEBUG
-	dbg_code = 0
+	// Initialize board-specific things.
+	board_init ()
 	#endif
 	must_wait = false
 	// Initialize kernel variables to empty.
@@ -266,8 +267,7 @@ void init (unsigned mem):
 	for unsigned i = 0; i < 32; ++i:
 		arch_interrupt_receiver[i] = NULL
 
-	// Initialize board-specific things.
-	board_init ()
+	// Enable timer interrupts.
 	intc_unmask_irq (TIMER_INTERRUPT)
 
 	// Say we're handling an exception.  Since we're going to enter the idle task, allow access to cp0.

mips/interrupts.ccp

@@ -251,6 +251,7 @@ kThread *exception ():
 			break
 		case 23:
 			// Reference to WatchHi/WatchLo address.
+			cp0_set0 (CP0_WATCH_LO)
 			current->raise (Kernel::ERR_WATCHPOINT, 0)
 			break
 		case 24:

mips/nanonote/board.ccp

@@ -21,28 +21,31 @@
 #include "kernel.hh"
 
 void board_init ():
-	unsigned cpm_uhccdr = CPM_UHCCDR
-	unsigned cpm_cpccr = CPM_CPCCR
-	unsigned cpm_cppcr = CPM_CPPCR
 	pll_init ()
 	cpm_stop_all ()
+	#ifndef NDEBUG
 	cpm_start_uart0 ()
-	cpm_start_tcu ()
-	cpm_start_lcd ()
 	gpio_as_uart0 ()
+	#endif
+	// Timer interrupts and buzzer.
+	cpm_start_tcu ()
+	// sdram memory.
 	gpio_as_sdram_16bit ()
+	// flash memory.
 	gpio_as_nand ()
+	// sound controller.
 	gpio_as_aic ()
+	// micro-sd controller.
 	gpio_as_msc ()
+	// display.
 	gpio_as_lcd_16bit ()
+	// buzzer.
 	gpio_as_pwm4 ()
 	// Set up memory.
 	setup_sdram ()
 	// Use some gpio pins for lcd.
 	gpio_as_gpio (2, (1 << 21) | (1 << 22) | (1 << 23))
-	gpio_as_gpio (3, 1 << 27)
 	gpio_as_output (2, (1 << 21) | (1 << 22) | (1 << 23))
-	gpio_as_output (3, 1 << 27)
 	// Set up keyboard: this breaks uart receive.
 	gpio_as_gpio (3, 0x05fc0000)
 	// Set up timed interrupts.
@@ -55,6 +58,7 @@ void board_init ():
 	tcu_clear_full_match_flag (0)
 	tcu_unmask_full_match_irq (0)
 	tcu_start_counter (0)
+	#ifndef NDEBUG
 	// Set up uart.
 	UART0_IER = 0
 	UART0_FCR = 0
@@ -68,12 +72,8 @@ void board_init ():
 	UART0_DLLR = uart_div
 	UART0_LCR = UARTLCR_WLEN_8 | UARTLCR_STOP1
 	UART0_FCR = UARTFCR_UUE | UARTFCR_FE | UARTFCR_RFLS | UARTFCR_TFLS
-	dbg_code.l = 1
 	dbg_log ("Serial port initialized\n")
-	dbg_log_num (CPM_CPCCR)
-	dbg_log ("+")
-	dbg_log_num (CPM_CPPCR)
-	dbg_log ("\n")
+	#endif
 
 void arch_reboot ():
 	// Wait for serial port to be done.

mips/nanonote/jz4740.hhp

@@ -102,7 +102,7 @@
 #define	ETH_BASE	0x00014000
 
 // Default lcd framebuffer mapping space.
-#define LCD_FRAMEBUFFER_BASE ((unsigned char *)0x00015000)
+#define LCD_FRAMEBUFFER_BASE ((unsigned *)0x00015000)
 
 // Map IO memory (requires a priviledged Kernel::my_thread capability).
 #include <iris.hh>
@@ -2347,9 +2347,10 @@ static void gpio_disable_pull (unsigned p, unsigned pins):
 //**************************************************************************
 static void pll_init ():
 	// The cpu clock frequency
-	//unsigned const cpu_clock = 336000000
-	unsigned const cpu_clock = 210000000
-	unsigned const pixclock = 27000000
+	unsigned const cpu_clock = 336000000
+	//unsigned const cpu_clock = 200000000
+	//unsigned const pixclock = 13500000
+	unsigned const pixclock = 25846153
 	// Configure the pll frequency to cpu_clock.
 	CPM_CPPCR = ((cpu_clock * 2 / JZ_EXTAL - 2) << CPM_CPPCR_PLLM_BIT) | (0 << CPM_CPPCR_PLLN_BIT) | (0 << CPM_CPPCR_PLLOD_BIT) | (0x20 << CPM_CPPCR_PLLST_BIT) | CPM_CPPCR_PLLEN
 	// Set up dividers; see documentation for the meaning of all the values.
@@ -3695,6 +3696,7 @@ static void setup_sdram ():
 	EMC_RTCSR = 0x83
 	EMC_RTCOR = 0x1f
 	#endif
+	#if 0
 	for unsigned i = 0; i < 5; ++i:
 		dbg_log ("memory: ")
 		dbg_log_num (EMC_SMCR (i), 8)
@@ -3705,6 +3707,7 @@ static void setup_sdram ():
 	dbg_log (",")
 	dbg_log_num (EMC_RTCOR, 8)
 	dbg_log ("\n")
+	#endif
 #endif
 
 #endif