qi-hardware/iris
1
0
Fork 0
mirror of git://projects.qi-hardware.com/iris.git synced 2025-04-21 12:27:27 +03:00
Code Activity

make more things work

Browse Source
This commit is contained in:
Bas Wijnen
2009-10-04 19:47:20 +02:00
parent 431b38acb9
commit 906f487b01
19 changed files with 872 additions and 268 deletions
Download Patch File Download Diff File Expand all files Collapse all files

12
mips/arch.ccp
View File

@@ -289,3 +289,15 @@ void arch_register_interrupt (unsigned num, kReceiver *r):
intc_unmask_irq (num)
else:
intc_mask_irq (num)
void arch_reboot ():
// Wait for serial port to be done.
while !(UART0_LSR & UARTLSR_TEMT):
// Reboot.
wdt_select_extalclk ()
wdt_select_clk_div1 ()
wdt_set_data (1)
wdt_set_count (0)
wdt_start ()
// Wait for wdt to trigger reboot.
while true:

8
mips/nanonote/Makefile.arch
View File

@@ -17,7 +17,7 @@
load = 0x80000000
ARCH_CXXFLAGS = -DNUM_THREADS=2
ARCH_CXXFLAGS = -DNUM_THREADS=4
ARCH_CPPFLAGS = -I. -Imips -Imips/nanonote -Wa,-mips32 -DNANONOTE -DUSE_SERIAL
CROSS = mipsel-linux-gnu-
OBJDUMP = $(CROSS)objdump
@@ -28,7 +28,7 @@ LDFLAGS = --omagic -Ttext $(load)
arch_iris_sources = mips/interrupts.cc mips/arch.cc
boot_sources = mips/init.cc mips/nanonote/board.cc
arch_headers = mips/arch.hh mips/nanonote/jz4740.hh mips/nanonote/board.hh
boot_threads = init udc
boot_threads = init udc nanonote-gpio buzzer
test: iris.raw nanonote-boot
./nanonote-boot iris.raw 0xa$(shell /bin/sh -c '$(OBJDUMP) -t iris.elf | grep __start$$ | cut -b2-8')
@@ -50,7 +50,7 @@ mips/entry.o: $(boot_threads)
mips/init.o: TARGET_FLAGS = -I/usr/include
$(boot_threads): TARGET_FLAGS = -I.
$(boot_threads): LDFLAGS = -EL
$(addprefix boot-programs/,$(addsuffix .cc,$(boot_threads))): boot-programs/devices.hh boot-programs/init.hh
$(addprefix boot-programs/,$(addsuffix .cc,$(boot_threads))): boot-programs/devices.hh
lcd: boot-programs/charset.data
boot-programs/charset.data: boot-programs/charset
@@ -63,4 +63,4 @@ boot-programs/charset.data: boot-programs/charset
iris.elf: mips/entry.o $(subst .cc,.o,$(iris_sources)) mips/nanonote/threadlist.o mips/boot.o $(subst .cc,.o,$(boot_sources))
$(LD) $(LDFLAGS) $^ -o $@
ARCH_CLEAN_FILES = $(boot_sources) $(boot_threads) $(arch_headers) boot_programs/init.hh boot_programs/devices.hh mips/*.o mips/nanonote/*.o boot-programs/charset.data iris.elf iris.raw mips/nanonote/sdram-setup.elf mips/nanonote/sdram-setup.raw
ARCH_CLEAN_FILES = $(boot_sources) $(boot_threads) $(arch_headers) boot_programs/devices.hh mips/*.o mips/nanonote/*.o boot-programs/charset.data iris.elf iris.raw mips/nanonote/sdram-setup.elf mips/nanonote/sdram-setup.raw

1
mips/nanonote/board.ccp
View File

@@ -29,6 +29,7 @@ void board_init ():
gpio_as_aic ()
gpio_as_lcd_16bit ()
gpio_as_msc ()
setup_sdram ()
// Set up keyboard: this breaks uart receive.
gpio_as_gpio (3, 0x05fc0000)
tcu_stop_counter (0)

103
mips/nanonote/jz4740.hhp
View File

@@ -117,7 +117,7 @@ static void __map_io (unsigned physical, unsigned mapping):
#define map_intc() do { __map_io (INTC_PHYSICAL, INTC_BASE); } while (0)
#define map_tcu() do { __map_io (TCU_PHYSICAL, TCU_BASE); } while (0)
#define map_wdt() do { __map_io (WDT_PHYSICAL, WDT_BASE); } while (0)
#define map_rtc() do { __map_io (RTC_PHYSICAL, RTC_BASE); } while (0)
#define map_rtc() do { __map_io (RTC_PHYSICAL, RTC_BASE); } while (1)
#define map_gpio() do { __map_io (GPIO_PHYSICAL, GPIO_BASE); } while (0)
#define map_aic() do { __map_io (AIC_PHYSICAL, AIC_BASE); } while (0)
#define map_uart0() do { __map_io (UART0_PHYSICAL, UART0_BASE); } while (0)
@@ -2322,7 +2322,7 @@ static void gpio_as_interrupt (unsigned p, unsigned pins, bool high, bool level)
if high:
GPIO_PXDIRS (p) = pins
else:
GPIO_PXDIRS (p) = pins
GPIO_PXDIRC (p) = pins
GPIO_PXFLGC (p) = pins
static void gpio_set (unsigned p, unsigned pins):
@@ -3577,4 +3577,103 @@ static void cim_enable_nongated_clock_mode ():
static void setup_sdram ():
// SDRAM BANK Number: 1, 2
unsigned CONFIG_NR_DRAM_BANKS = 1
// CAS latency: 2 or 3
unsigned SDRAM_CASL = 3
// SDRAM Timings, unit: ns
// RAS# Active Time
unsigned SDRAM_TRAS = 45
// RAS# to CAS# Delay
unsigned SDRAM_RCD = 20
// RAS# Precharge Time
unsigned SDRAM_TPC = 20
// Write Latency Time
unsigned SDRAM_TRWL = 7
// Refresh period: 4096 refresh cycles/64ms
unsigned SDRAM_TREF = 15625
unsigned dmcr0, dmcr, sdmode, tmp, cpu_clk, mem_clk, ns
unsigned cas_latency_sdmr[2] = { EMC_SDMR_CAS_2, EMC_SDMR_CAS_3 }
unsigned cas_latency_dmcr[2] = { 1 << EMC_DMCR_TCL_BIT, 2 << EMC_DMCR_TCL_BIT }
int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32}
cpu_clk = 225000000
gpio_as_sdram_32bit ()
unsigned SDRAM_BW16 = 0
unsigned SDRAM_BANK4 = 1
unsigned SDRAM_ROW = 13
unsigned SDRAM_COL = 9
mem_clk = cpu_clk * div[cpm_get_cdiv()] / div[cpm_get_mdiv()]
EMC_BCR = 0
EMC_RTCSR = 0
unsigned SDRAM_ROW0 = 11
unsigned SDRAM_COL0 = 8
unsigned SDRAM_BANK40 = 0
dmcr0 = ((SDRAM_ROW0-11)<<EMC_DMCR_RA_BIT) | ((SDRAM_COL0-8)<<EMC_DMCR_CA_BIT) | (SDRAM_BANK40<<EMC_DMCR_BA_BIT) | (SDRAM_BW16<<EMC_DMCR_BW_BIT) | EMC_DMCR_EPIN | cas_latency_dmcr[((SDRAM_CASL == 3) ? 1 : 0)]
// Basic DMCR value
dmcr = ((SDRAM_ROW-11)<<EMC_DMCR_RA_BIT) | ((SDRAM_COL-8)<<EMC_DMCR_CA_BIT) | (SDRAM_BANK4<<EMC_DMCR_BA_BIT) | (SDRAM_BW16<<EMC_DMCR_BW_BIT) | EMC_DMCR_EPIN | cas_latency_dmcr[((SDRAM_CASL == 3) ? 1 : 0)]
// SDRAM timimg
ns = 1000000000 / mem_clk
tmp = SDRAM_TRAS / ns
if tmp < 4:
tmp = 4
if tmp > 11:
tmp = 11
dmcr |= ((tmp-4) << EMC_DMCR_TRAS_BIT)
tmp = SDRAM_RCD/ns
if tmp > 3:
tmp = 3
dmcr |= (tmp << EMC_DMCR_RCD_BIT)
tmp = SDRAM_TPC/ns
if tmp > 7:
tmp = 7
dmcr |= (tmp << EMC_DMCR_TPC_BIT)
tmp = SDRAM_TRWL/ns
if tmp > 3:
tmp = 3
dmcr |= (tmp << EMC_DMCR_TRWL_BIT)
tmp = (SDRAM_TRAS + SDRAM_TPC)/ns
if tmp > 14:
tmp = 14
dmcr |= (((tmp + 1) >> 1) << EMC_DMCR_TRC_BIT)
// SDRAM mode value
sdmode = EMC_SDMR_BT_SEQ | EMC_SDMR_OM_NORMAL | EMC_SDMR_BL_4 | cas_latency_sdmr[((SDRAM_CASL == 3) ? 1 : 0)];
// Stage 1. Precharge all banks by writing SDMR with DMCR.MRSET=0
EMC_DMCR = dmcr
REG8(EMC_SDMR0|sdmode) = 0
// Wait for precharge, > 200us
tmp = (cpu_clk / 1000000) * 1000
volatile unsigned t = tmp
while t--:
// Stage 2. Enable auto-refresh
EMC_DMCR = dmcr | EMC_DMCR_RFSH
tmp = SDRAM_TREF/ns
tmp = tmp/64 + 1
if tmp > 0xff:
tmp = 0xff
EMC_RTCOR = tmp
EMC_RTCNT = 0
// Divisor is 64, CKO/64
EMC_RTCSR = EMC_RTCSR_CKS_64
// Wait for number of auto-refresh cycles
tmp = (cpu_clk / 1000000) * 1000
t = tmp
while t--:
// Stage 3. Mode Register Set
EMC_DMCR = dmcr0 | EMC_DMCR_RFSH | EMC_DMCR_MRSET
REG8(EMC_SDMR0|sdmode) = 0
// Set back to basic DMCR value
EMC_DMCR = dmcr | EMC_DMCR_RFSH | EMC_DMCR_MRSET
#endif

17
mips/nanonote/nanonote-boot.ccp
View File

@@ -132,6 +132,13 @@ nanonote::nanonote (unsigned skip):
if !find_device (skip):
std::cerr << "unable to find NanoNote device.\n";
throw "unable to find NanoNote device";
// Get info will reset the device if it has already booted into Iris.
get_cpu_info ()
usb_close (handle)
sleep (1)
if !find_device (skip):
std::cerr << "unable to find NanoNote device again.\n";
throw "unable to find NanoNote device again";
void nanonote::get_cpu_info ():
char buffer[8]
@@ -141,14 +148,12 @@ void nanonote::get_cpu_info ():
cpu_info = std::string (buffer, 8)
void nanonote::request (requests r, unsigned data):
std::cerr << "requesting " << r << " (data = " << std::hex << data << ")" << std::endl
if usb_control_msg (handle, USB_ENDPOINT_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE, r, (data >> 16) & 0xffff, data & 0xffff, NULL, 0, timeout) < 0:
std::cerr << "unable to send control message to NanoNote: " << usb_strerror () << ".\n"
throw "unable to send control message to NanoNote"
void nanonote::send_file (unsigned address, unsigned size, char const *data):
request (VR_SET_DATA_ADDRESS, address)
//request (VR_SET_DATA_LENGTH, size)
char const *ptr = data
while ptr - data < size:
int ret = usb_bulk_write (handle, out_ep, ptr, size - (ptr - data), timeout)
@@ -158,20 +163,12 @@ void nanonote::send_file (unsigned address, unsigned size, char const *data):
ptr += ret
void nanonote::boot (std::string const &data, unsigned load, unsigned start):
get_cpu_info ()
std::cerr << "info: " << cpu_info << std::endl
send_file (stage1_load, stage1_size, stage1)
request (VR_PROGRAM_START1, stage1_start)
usleep (100)
send_file (load, data.size (), data.data ())
request (VR_FLUSH_CACHES)
request (VR_PROGRAM_START2, start)
sleep (1)
get_cpu_info ()
std::cerr << "info: ";
for unsigned i = 0; i < cpu_info.size (); ++i:
std::cerr << std::setfill ('0') << std::setw (2) << std::hex << (cpu_info[i] & 0xff);
std::cerr << std::endl
int main (int argc, char **argv):
if argc != 3:

108
mips/nanonote/sdram-setup.ccp
View File

@@ -20,15 +20,6 @@
#define __KERNEL
#include "jz4740.hh"
#define CONFIG_NR_DRAM_BANKS 1 // SDRAM BANK Number: 1, 2
#define SDRAM_CASL 3 // CAS latency: 2 or 3
// SDRAM Timings, unit: ns
#define SDRAM_TRAS 45 // RAS# Active Time
#define SDRAM_RCD 20 // RAS# to CAS# Delay
#define SDRAM_TPC 20 // RAS# Precharge Time
#define SDRAM_TRWL 7 // Write Latency Time
#define SDRAM_TREF 15625 // Refresh period: 4096 refresh cycles/64ms
asm volatile (".set noreorder\n"
"\t.globl __start\n"
"\t.text\n"
@@ -51,102 +42,5 @@ extern "C":
void start_cpp ()
void start_cpp ():
unsigned dmcr0, dmcr, sdmode, tmp, cpu_clk, mem_clk, ns
unsigned cas_latency_sdmr[2] = { EMC_SDMR_CAS_2, EMC_SDMR_CAS_3 }
unsigned cas_latency_dmcr[2] = { 1 << EMC_DMCR_TCL_BIT, 2 << EMC_DMCR_TCL_BIT }
int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32}
cpu_clk = 225000000
gpio_as_sdram_32bit ()
unsigned SDRAM_BW16 = 0
unsigned SDRAM_BANK4 = 1
unsigned SDRAM_ROW = 13
unsigned SDRAM_COL = 9
mem_clk = cpu_clk * div[cpm_get_cdiv()] / div[cpm_get_mdiv()]
EMC_BCR = 0
EMC_RTCSR = 0
#define SDRAM_ROW0 11
#define SDRAM_COL0 8
#define SDRAM_BANK40 0
dmcr0 = ((SDRAM_ROW0-11)<<EMC_DMCR_RA_BIT) | ((SDRAM_COL0-8)<<EMC_DMCR_CA_BIT) | (SDRAM_BANK40<<EMC_DMCR_BA_BIT) | (SDRAM_BW16<<EMC_DMCR_BW_BIT) | EMC_DMCR_EPIN | cas_latency_dmcr[((SDRAM_CASL == 3) ? 1 : 0)]
// Basic DMCR value
dmcr = ((SDRAM_ROW-11)<<EMC_DMCR_RA_BIT) | ((SDRAM_COL-8)<<EMC_DMCR_CA_BIT) | (SDRAM_BANK4<<EMC_DMCR_BA_BIT) | (SDRAM_BW16<<EMC_DMCR_BW_BIT) | EMC_DMCR_EPIN | cas_latency_dmcr[((SDRAM_CASL == 3) ? 1 : 0)]
// SDRAM timimg
ns = 1000000000 / mem_clk
tmp = SDRAM_TRAS / ns
if tmp < 4:
tmp = 4
if tmp > 11:
tmp = 11
dmcr |= ((tmp-4) << EMC_DMCR_TRAS_BIT)
tmp = SDRAM_RCD/ns
if tmp > 3:
tmp = 3
dmcr |= (tmp << EMC_DMCR_RCD_BIT)
tmp = SDRAM_TPC/ns
if tmp > 7:
tmp = 7
dmcr |= (tmp << EMC_DMCR_TPC_BIT)
tmp = SDRAM_TRWL/ns
if tmp > 3:
tmp = 3
dmcr |= (tmp << EMC_DMCR_TRWL_BIT)
tmp = (SDRAM_TRAS + SDRAM_TPC)/ns
if tmp > 14:
tmp = 14
dmcr |= (((tmp + 1) >> 1) << EMC_DMCR_TRC_BIT)
// SDRAM mode value
sdmode = EMC_SDMR_BT_SEQ | EMC_SDMR_OM_NORMAL | EMC_SDMR_BL_4 | cas_latency_sdmr[((SDRAM_CASL == 3) ? 1 : 0)];
// Stage 1. Precharge all banks by writing SDMR with DMCR.MRSET=0
EMC_DMCR = dmcr
REG8(EMC_SDMR0|sdmode) = 0
// Wait for precharge, > 200us
tmp = (cpu_clk / 1000000) * 1000
volatile unsigned t = tmp
while t--:
// Stage 2. Enable auto-refresh
EMC_DMCR = dmcr | EMC_DMCR_RFSH
tmp = SDRAM_TREF/ns
tmp = tmp/64 + 1
if tmp > 0xff:
tmp = 0xff
EMC_RTCOR = tmp
EMC_RTCNT = 0
// Divisor is 64, CKO/64
EMC_RTCSR = EMC_RTCSR_CKS_64
// Wait for number of auto-refresh cycles
tmp = (cpu_clk / 1000000) * 1000
t = tmp
while t--:
// Stage 3. Mode Register Set
EMC_DMCR = dmcr0 | EMC_DMCR_RFSH | EMC_DMCR_MRSET
REG8(EMC_SDMR0|sdmode) = 0
// Set back to basic DMCR value
EMC_DMCR = dmcr | EMC_DMCR_RFSH | EMC_DMCR_MRSET
setup_sdram ()
// everything is ok now: return to boot loader to load stage 2.
pll_init ()
cpm_start_all ()
gpio_as_uart0 ()
UART0_IER = 0
UART0_FCR = 0
UART0_MCR = 0
UART0_SIRCR = 0
UART0_UMR = 0
UART0_UACR = 0
UART0_LCR = UARTLCR_WLEN_8 | UARTLCR_STOP1 | UARTLCR_DLAB
unsigned uart_div = 3000000 / 16 / 9600
UART0_DLHR = uart_div >> 8
UART0_DLLR = uart_div
UART0_LCR = UARTLCR_WLEN_8 | UARTLCR_STOP1
UART0_FCR = UARTFCR_UUE | UARTFCR_FE | UARTFCR_RFLS | UARTFCR_TFLS

10
mips/nanonote/threadlist.S
View File

@@ -27,7 +27,15 @@ thread0:
thread1:
.incbin "udc"
.balign 0x1000
thread2:
.incbin "nanonote-gpio"
.balign 0x1000
thread3:
.incbin "buzzer"
thread4:
// Everything from here may be freed after kernel initialization.
init_start:
@@ -36,3 +44,5 @@ thread_start:
.word thread0
.word thread1
.word thread2
.word thread3
.word thread4