split off nanonote code, try to make it boot

mips/nanonote/Makefile.arch

@@ -0,0 +1,66 @@
+# Iris: micro-kernel for a capability-based operating system.
+# mips/nanonote/Makefile.arch: nanonote-specific parts of the build rules
+# Copyright 2009 Bas Wijnen <wijnen@debian.org>
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+
+load = 0x80000000
+
+ARCH_CXXFLAGS = -DNUM_THREADS=2
+ARCH_CPPFLAGS = -I. -Imips -Imips/nanonote -Wa,-mips32 -DNANONOTE
+CROSS = mipsel-linux-gnu-
+OBJDUMP = $(CROSS)objdump
+junk = mdebug.abi32 reginfo comment pdr
+OBJCOPYFLAGS = $(addprefix --remove-section=.,$(junk))
+LDFLAGS = --omagic -Ttext $(load)
+
+arch_iris_sources = mips/interrupts.cc mips/arch.cc
+boot_sources = mips/init.cc mips/nanonote/board.cc
+arch_headers = mips/arch.hh mips/nanonote/jz4740.hh mips/nanonote/board.hh
+boot_threads = init udc
+
+test: iris.raw nanonote-boot
+	./nanonote-boot iris.raw 0xa$(shell /bin/sh -c '$(OBJDUMP) -t iris | grep __start$$ | cut -b2-8')
+.PHONY: test
+
+%.elf: %.o
+	$(LD) $(LDFLAGS) -o $@ $<
+
+%.raw: %.elf
+	$(OBJCOPY) -S $(OBJCOPYFLAGS) -Obinary $< $@
+
+nanonote-boot: mips/nanonote/nanonote-boot.cc mips/nanonote/sdram-setup.raw
+	g++ `pkg-config --cflags --libs shevek` $< -o $@ -D'STAGE1="$<"' -lusb
+
+mips/nanonote/sdram-setup.elf: mips/nanonote/sdram-setup.ld
+mips/nanonote/sdram-setup.elf: LDFLAGS = --omagic -T mips/nanonote/sdram-setup.ld
+mips/boot.o: TARGET_FLAGS = -DMEMORY_SIZE="32 << 20"
+mips/entry.o: $(boot_threads)
+mips/init.o: TARGET_FLAGS = -I/usr/include
+$(boot_threads): TARGET_FLAGS = -I.
+$(boot_threads): LDFLAGS = -EL
+$(addprefix boot-programs/,$(addsuffix .cc,$(boot_threads))): boot-programs/devices.hh boot-programs/init.hh
+lcd: boot-programs/charset.data
+
+boot-programs/charset.data: boot-programs/charset
+	$< > $@
+
+%.o:%.S Makefile Makefile.arch mips/arch.hh
+	$(CC) $(CPPFLAGS) $(TARGET_FLAGS) -DKERNEL_STACK_SIZE=0x2000 -c $< -o $@
+
+# entry.o must be the first file.  threadlist.o must be the first of the init objects (which can be freed after loading).
+iris.elf: mips/entry.o $(subst .cc,.o,$(iris_sources)) mips/nanonote/threadlist.o mips/boot.o $(subst .cc,.o,$(boot_sources))
+	$(LD) $(LDFLAGS) $^ -o $@
+
+ARCH_CLEAN_FILES = $(boot_sources) $(boot_threads) $(arch_headers) boot_programs/init.hh boot_programs/devices.hh mips/*.o mips/nanonote/*.o boot-programs/charset.data iris.elf iris.raw mips/nanonote/sdram-setup.elf mips/nanonote/sdram-setup.raw

mips/nanonote/board.ccp

@@ -0,0 +1,51 @@
+#pypp 0
+// Iris: micro-kernel for a capability-based operating system.
+// mips/nanonote/board.ccp: nanonote-specific definitions.
+// Copyright 2009 Bas Wijnen <wijnen@debian.org>
+//
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program.  If not, see <http://www.gnu.org/licenses/>.
+
+#define ARCH
+#define INIT
+#include "kernel.hh"
+
+void board_init ():
+	cpm_start_all ()
+	gpio_as_uart0 ()
+	gpio_as_sdram_16bit ()
+	gpio_as_nand ()
+	gpio_as_aic ()
+	gpio_as_lcd_16bit ()
+	gpio_as_msc ()
+	// Set up keyboard: this breaks uart receive.
+	gpio_as_gpio (3, 0x05fc0000)
+	tcu_stop_counter (0)
+	tcu_select_extalclk (0)
+	tcu_select_clk_div1 (0)
+	tcu_disable_pwm_output (0)
+	tcu_set_full_data (0, JZ_EXTAL / HZ)
+	tcu_mask_half_match_irq (0)
+	tcu_clear_full_match_flag (0)
+	tcu_unmask_full_match_irq (0)
+	tcu_start_counter (0)
+	// Set up uart.
+	uart_disable (0)
+	uart_set_baud (0, JZ_EXTAL, 9600)
+	uart_set_8n1 (0)
+	UART0_IER = 0
+	UART0_MCR = 0
+	UART0_SIRCR = 0
+	UART0_UMR = 0
+	UART0_UACR = 0
+	UART0_FCR |= UARTFCR_UUE | UARTFCR_RFLS | UARTFCR_TFLS

mips/nanonote/board.hhp

@@ -0,0 +1,19 @@
+#pypp 0
+// Iris: micro-kernel for a capability-based operating system.
+// mips/nanonote/board.hhp: nanonote-specific declarations and type definitions.
+// Copyright 2009 Bas Wijnen <wijnen@debian.org>
+//
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program.  If not, see <http://www.gnu.org/licenses/>.
+
+#include "jz4740.hh"

mips/nanonote/nanonote-boot.ccp

@@ -0,0 +1,188 @@
+#pypp 0
+// Iris: micro-kernel for a capability-based operating system.
+// mips/nanonote/nanonote-boot.ccp: Host-side helper for booting over USB.
+// Copyright 2009 Bas Wijnen <wijnen@debian.org>
+//
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program.  If not, see <http://www.gnu.org/licenses/>.
+
+#include <unistd.h>
+#include <usb.h>
+#include <fstream>
+#include <sstream>
+#include <iostream>
+
+asm volatile (".section .rodata\n"
+	".globl stage1\n"
+	".globl stage1_end\n"
+	"stage1:\n"
+	".incbin \"mips/nanonote/sdram-setup.raw\"\n"
+	"stage1_end:\n"
+	".section .text")
+extern char stage1[1]
+extern char stage1_end[1]
+
+unsigned const stage1_load = 0x80002000
+unsigned const stage1_start = 0x80002000
+unsigned const stage1_size = stage1_end - stage1
+
+class nanonote:
+	public:
+
+	nanonote (unsigned skip = 0)
+	void boot (std::string const &data, unsigned load, unsigned start)
+
+	private:
+
+	enum requests:
+		VR_GET_CPU_INFO		= 0
+		VR_SET_DATA_ADDRESS	= 1
+		VR_SET_DATA_LENGTH	= 2
+		VR_FLUSH_CACHES		= 3
+		VR_PROGRAM_START1	= 4
+		VR_PROGRAM_START2	= 5
+	static int const vendor = 0x601a
+	static int const product = 0x4740
+	static unsigned const timeout = 1000
+	usb_dev_handle *handle
+	int interface
+	int in_ep, out_ep
+	std::string cpu_info
+	bool try_open (struct usb_device *dev)
+	bool find_device (unsigned skip)
+	void request (requests num, unsigned data = 0)
+	void send_file (unsigned address, unsigned size, char const *data)
+	void get_cpu_info ()
+
+bool nanonote::try_open (struct usb_device *dev):
+	handle = usb_open (dev)
+
+	if dev->descriptor.bNumConfigurations != 1:
+		usb_close (handle)
+		std::cerr << dev->descriptor.bNumConfigurations << " configurations\n"
+		return false
+	if usb_set_configuration (handle, 1) < 0:
+		usb_close (handle)
+		std::cerr << "Can't set configuration 1: " << usb_strerror () << '\n'
+		return false
+
+	interface = dev->config->interface->altsetting->bInterfaceNumber
+	int have_in = 0, have_out = 0
+	for unsigned i = 0; i < dev->config->interface->altsetting->bNumEndpoints; ++i:
+		if (dev->config->interface->altsetting->endpoint[i].bmAttributes & USB_ENDPOINT_TYPE_MASK) != USB_ENDPOINT_TYPE_BULK:
+			usb_close (handle)
+			std::cerr << "Device has non-bulk endpoint.\n"
+			return false
+		if (dev->config->interface->altsetting->endpoint[i].bEndpointAddress & USB_ENDPOINT_DIR_MASK):
+			/* input */
+			if have_in:
+				usb_close (handle)
+				std::cerr << "Device has multiple IN endpoints.\n"
+				return false
+			have_in = 1
+			in_ep = dev->config->interface->altsetting->endpoint[i].bEndpointAddress & USB_ENDPOINT_ADDRESS_MASK
+			if in_ep != 1:
+				usb_close (handle)
+				std::cerr << "IN endpoint is not numbered as 1.\n"
+				return false
+		else:
+			/* output */
+			if have_out:
+				usb_close (handle)
+				std::cerr << "Device has multiple OUT endpoints.\n"
+				return false
+			have_out = 1
+			out_ep = dev->config->interface->altsetting->endpoint[i].bEndpointAddress & USB_ENDPOINT_ADDRESS_MASK
+			if out_ep != 1:
+				usb_close (handle)
+				std::cerr << "OUT endpoint is not numbered as 1.\n"
+				return false
+	if usb_claim_interface (handle, interface) < 0:
+		std::cerr << "unable to claim interface\n"
+		return false
+	return true
+
+bool nanonote::find_device (unsigned skip):
+	unsigned skipped = 0
+	usb_init ()
+	usb_find_busses ()
+	usb_find_devices ()
+	for struct usb_bus *bus = usb_busses; bus; bus = bus->next:
+		for struct usb_device *dev = bus->devices; dev; dev = dev->next:
+			if dev->descriptor.idProduct != product || dev->descriptor.idVendor != vendor:
+				continue
+			if skip > skipped++:
+				continue
+			if try_open (dev):
+				return true
+	return false
+
+nanonote::nanonote (unsigned skip):
+	if !find_device (skip):
+		std::cerr << "unable to find NanoNote device.\n";
+		throw "unable to find NanoNote device";
+
+void nanonote::get_cpu_info ():
+	char buffer[8]
+	if usb_control_msg (handle, USB_ENDPOINT_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE, VR_GET_CPU_INFO, 0, 0, buffer, 8, timeout) < 0:
+		std::cerr << "unable to request cpu info from NanoNote: " << usb_strerror () << ".\n"
+		throw "unable to request cpu info from NanoNote"
+	cpu_info = std::string (buffer, 8)
+
+void nanonote::request (requests r, unsigned data):
+	std::cerr << "requesting " << r << " (data = " << std::hex << data << ")" << std::endl
+	if usb_control_msg (handle, USB_ENDPOINT_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE, r, (data >> 16) & 0xffff, data & 0xffff, NULL, 0, timeout) < 0:
+		std::cerr << "unable to send control message to NanoNote: " << usb_strerror () << ".\n"
+		throw "unable to send control message to NanoNote"
+
+void nanonote::send_file (unsigned address, unsigned size, char const *data):
+	request (VR_SET_DATA_ADDRESS, address)
+	//request (VR_SET_DATA_LENGTH, size)
+	char const *ptr = data
+	while ptr - data < size:
+		int ret = usb_bulk_write (handle, out_ep, ptr, size - (ptr - data), timeout)
+		if ret <= 0:
+			std::cerr << "failed to write to NanoNote.\n"
+			throw "failed to write to NanoNote"
+		ptr += ret
+
+void nanonote::boot (std::string const &data, unsigned load, unsigned start):
+	get_cpu_info ()
+	std::cerr << "info: " << cpu_info << std::endl
+	send_file (stage1_load, stage1_size, stage1)
+	request (VR_PROGRAM_START1, stage1_start)
+	usleep (100)
+	send_file (load, data.size (), data.data ())
+	request (VR_FLUSH_CACHES)
+	request (VR_PROGRAM_START2, start)
+	get_cpu_info ()
+	std::cerr << "info: " << cpu_info << std::endl
+
+int main (int argc, char **argv):
+	if argc != 3:
+		std::cerr << "Usage: " << argv[0] << " [kernel] [entry address]\n"
+		std::cerr << "The kernel is loaded from 0x80000000 and run from entry address\n"
+		return 1
+	unsigned entry = strtoul (argv[2], NULL, 0)
+	nanonote nn
+	std::ifstream file (argv[1])
+	if !file:
+		std::cerr << "can't open file '" << argv[1] << "' for reading.\n"
+		return 1
+	std::ostringstream data
+	data << file.rdbuf ()
+	if data.str ().empty ():
+		std::cerr << "no data read from '" << argv[1] << "'.\n"
+		return 1
+	nn.boot (data.str (), 0x80000000, entry)
+	return 0

mips/nanonote/sdram-setup.ccp

@@ -0,0 +1,136 @@
+#pypp 0
+// Iris: micro-kernel for a capability-based operating system.
+// mips/nanonote/sdram-setup.ccp: bootstrapping over usb.
+// Copyright 2009 Bas Wijnen <wijnen@debian.org>
+//
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program.  If not, see <http://www.gnu.org/licenses/>.
+
+// This runs like the kernel.  In particular, it doesn't want userspace declarations.
+#define __KERNEL
+#include "jz4740.hh"
+
+#define CONFIG_NR_DRAM_BANKS    1       // SDRAM BANK Number: 1, 2
+#define SDRAM_CASL              3       // CAS latency: 2 or 3
+// SDRAM Timings, unit: ns
+#define SDRAM_TRAS              45      // RAS# Active Time
+#define SDRAM_RCD               20      // RAS# to CAS# Delay
+#define SDRAM_TPC               20      // RAS# Precharge Time
+#define SDRAM_TRWL              7       // Write Latency Time
+#define SDRAM_TREF              15625   // Refresh period: 4096 refresh cycles/64ms
+
+asm volatile (".set noreorder\n"
+		"\t.globl __start\n"
+		"\t.text\n"
+		"__start:\n"
+		"\tla $sp, 0x80004000\n"
+		"__hack_label:\n"
+		"\tmove $a0, $ra\n"
+		"\tbal 1f\n"
+		"\tnop\n"
+		"\t.word _gp\n"
+		"1:\n"
+		"\tlw $gp, 0($ra)\n"
+		"\tla $t9, start_cpp\n"
+		"\tmove $ra, $a0\n"
+		"\tjr $t9\n"
+		"\tnop\n"
+		".set reorder")
+
+extern "C":
+	void start_cpp ()
+
+void start_cpp ():
+	unsigned dmcr0, dmcr, sdmode, tmp, cpu_clk, mem_clk, ns
+	unsigned cas_latency_sdmr[2] = { EMC_SDMR_CAS_2, EMC_SDMR_CAS_3 }
+	unsigned cas_latency_dmcr[2] = { 1 << EMC_DMCR_TCL_BIT, 2 << EMC_DMCR_TCL_BIT }
+	int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32}
+
+	cpu_clk = 225000000
+	gpio_as_sdram_32bit ()
+	unsigned SDRAM_BW16 = 0
+	unsigned SDRAM_BANK4 = 1
+	unsigned SDRAM_ROW = 13
+	unsigned SDRAM_COL = 9
+
+	mem_clk = cpu_clk * div[cpm_get_cdiv()] / div[cpm_get_mdiv()]
+	EMC_BCR = 0
+	EMC_RTCSR = 0
+	#define SDRAM_ROW0    11
+	#define SDRAM_COL0     8
+	#define SDRAM_BANK40   0
+	dmcr0 = ((SDRAM_ROW0-11)<<EMC_DMCR_RA_BIT) | ((SDRAM_COL0-8)<<EMC_DMCR_CA_BIT) | (SDRAM_BANK40<<EMC_DMCR_BA_BIT) | (SDRAM_BW16<<EMC_DMCR_BW_BIT) | EMC_DMCR_EPIN | cas_latency_dmcr[((SDRAM_CASL == 3) ? 1 : 0)]
+	// Basic DMCR value
+	dmcr = ((SDRAM_ROW-11)<<EMC_DMCR_RA_BIT) | ((SDRAM_COL-8)<<EMC_DMCR_CA_BIT) | (SDRAM_BANK4<<EMC_DMCR_BA_BIT) | (SDRAM_BW16<<EMC_DMCR_BW_BIT) | EMC_DMCR_EPIN | cas_latency_dmcr[((SDRAM_CASL == 3) ? 1 : 0)]
+	// SDRAM timimg
+	ns = 1000000000 / mem_clk
+	tmp = SDRAM_TRAS / ns
+	if tmp < 4:
+		tmp = 4
+	if tmp > 11:
+		tmp = 11
+	dmcr |= ((tmp-4) << EMC_DMCR_TRAS_BIT)
+	tmp = SDRAM_RCD/ns
+	if tmp > 3:
+		tmp = 3
+	dmcr |= (tmp << EMC_DMCR_RCD_BIT)
+	tmp = SDRAM_TPC/ns
+	if tmp > 7:
+		tmp = 7
+	dmcr |= (tmp << EMC_DMCR_TPC_BIT)
+	tmp = SDRAM_TRWL/ns
+	if tmp > 3:
+		tmp = 3
+	dmcr |= (tmp << EMC_DMCR_TRWL_BIT)
+	tmp = (SDRAM_TRAS + SDRAM_TPC)/ns
+	if tmp > 14:
+		tmp = 14
+	dmcr |= (((tmp + 1) >> 1) << EMC_DMCR_TRC_BIT)
+
+	// SDRAM mode value
+	sdmode = EMC_SDMR_BT_SEQ | EMC_SDMR_OM_NORMAL | EMC_SDMR_BL_4 | cas_latency_sdmr[((SDRAM_CASL == 3) ? 1 : 0)];
+
+	// Stage 1. Precharge all banks by writing SDMR with DMCR.MRSET=0
+	EMC_DMCR = dmcr
+	REG8(EMC_SDMR0|sdmode) = 0
+
+	// Wait for precharge, > 200us
+	tmp = (cpu_clk / 1000000) * 1000
+	volatile unsigned t = tmp
+	while t--:
+
+	// Stage 2. Enable auto-refresh
+	EMC_DMCR = dmcr | EMC_DMCR_RFSH
+
+	tmp = SDRAM_TREF/ns
+	tmp = tmp/64 + 1
+	if tmp > 0xff:
+		tmp = 0xff
+	EMC_RTCOR = tmp
+	EMC_RTCNT = 0
+	// Divisor is 64, CKO/64
+	EMC_RTCSR = EMC_RTCSR_CKS_64
+
+	// Wait for number of auto-refresh cycles
+	tmp = (cpu_clk / 1000000) * 1000
+	t = tmp
+	while t--:
+
+	// Stage 3. Mode Register Set
+	EMC_DMCR = dmcr0 | EMC_DMCR_RFSH | EMC_DMCR_MRSET
+	REG8(EMC_SDMR0|sdmode) = 0
+
+	// Set back to basic DMCR value
+	EMC_DMCR = dmcr | EMC_DMCR_RFSH | EMC_DMCR_MRSET
+
+	// everything is ok now: return to boot loader to load stage 2.

mips/nanonote/sdram-setup.ld

@@ -0,0 +1,31 @@
+OUTPUT_ARCH(mips)
+ENTRY(__start)
+MEMORY
+{
+	ram	: ORIGIN = 0x80002000 , LENGTH = 0x100000
+}
+
+SECTIONS
+{
+	. = ALIGN(4);
+	.text : { *(.text*) } > ram
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata*) } > ram
+
+	. = ALIGN(4);
+	.sdata : { *(.sdata*) } > ram
+
+	. = ALIGN(4);
+	.data : { *(.data*) *(.scommon*) *(.reginfo*) } > ram
+
+	_gp = ABSOLUTE(.); /* Base of small data */
+
+	.got : { *(.got*) } > ram
+
+	. = ALIGN(4);
+	.sbss : { *(.sbss*) } > ram
+	.bss : { *(.bss*) } > ram
+	. = ALIGN (4);
+}
+

mips/nanonote/threadlist.S

@@ -0,0 +1,38 @@
+// Iris: micro-kernel for a capability-based operating system.
+// mips/nanonote/threadlist.S: List of initial threads.
+// Copyright 2009 Bas Wijnen <wijnen@debian.org>
+//
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program.  If not, see <http://www.gnu.org/licenses/>.
+
+	.globl init_start
+	.globl thread_start
+	.set noreorder
+
+	.balign 0x1000
+thread0:
+	.incbin "init"
+
+	.balign 0x1000
+thread1:
+	.incbin "udc"
+
+thread2:
+
+// Everything from here may be freed after kernel initialization.
+init_start:
+
+thread_start:
+	.word thread0
+	.word thread1
+	.word thread2