mirror of
git://projects.qi-hardware.com/iris.git
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137 lines
4.2 KiB
COBOL
137 lines
4.2 KiB
COBOL
#pypp 0
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// Iris: micro-kernel for a capability-based operating system.
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// mips/nanonote/sdram-setup.ccp: bootstrapping over usb.
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// Copyright 2009 Bas Wijnen <wijnen@debian.org>
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//
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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// This runs like the kernel. In particular, it doesn't want userspace declarations.
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#define __KERNEL
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#include "jz4740.hh"
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#define CONFIG_NR_DRAM_BANKS 1 // SDRAM BANK Number: 1, 2
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#define SDRAM_CASL 3 // CAS latency: 2 or 3
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// SDRAM Timings, unit: ns
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#define SDRAM_TRAS 45 // RAS# Active Time
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#define SDRAM_RCD 20 // RAS# to CAS# Delay
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#define SDRAM_TPC 20 // RAS# Precharge Time
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#define SDRAM_TRWL 7 // Write Latency Time
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#define SDRAM_TREF 15625 // Refresh period: 4096 refresh cycles/64ms
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asm volatile (".set noreorder\n"
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"\t.globl __start\n"
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"\t.text\n"
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"__start:\n"
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"\tla $sp, 0x80004000\n"
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"__hack_label:\n"
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"\tmove $a0, $ra\n"
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"\tbal 1f\n"
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"\tnop\n"
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"\t.word _gp\n"
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"1:\n"
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"\tlw $gp, 0($ra)\n"
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"\tla $t9, start_cpp\n"
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"\tmove $ra, $a0\n"
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"\tjr $t9\n"
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"\tnop\n"
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".set reorder")
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extern "C":
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void start_cpp ()
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void start_cpp ():
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unsigned dmcr0, dmcr, sdmode, tmp, cpu_clk, mem_clk, ns
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unsigned cas_latency_sdmr[2] = { EMC_SDMR_CAS_2, EMC_SDMR_CAS_3 }
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unsigned cas_latency_dmcr[2] = { 1 << EMC_DMCR_TCL_BIT, 2 << EMC_DMCR_TCL_BIT }
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int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32}
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cpu_clk = 225000000
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gpio_as_sdram_32bit ()
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unsigned SDRAM_BW16 = 0
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unsigned SDRAM_BANK4 = 1
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unsigned SDRAM_ROW = 13
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unsigned SDRAM_COL = 9
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mem_clk = cpu_clk * div[cpm_get_cdiv()] / div[cpm_get_mdiv()]
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EMC_BCR = 0
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EMC_RTCSR = 0
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#define SDRAM_ROW0 11
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#define SDRAM_COL0 8
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#define SDRAM_BANK40 0
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dmcr0 = ((SDRAM_ROW0-11)<<EMC_DMCR_RA_BIT) | ((SDRAM_COL0-8)<<EMC_DMCR_CA_BIT) | (SDRAM_BANK40<<EMC_DMCR_BA_BIT) | (SDRAM_BW16<<EMC_DMCR_BW_BIT) | EMC_DMCR_EPIN | cas_latency_dmcr[((SDRAM_CASL == 3) ? 1 : 0)]
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// Basic DMCR value
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dmcr = ((SDRAM_ROW-11)<<EMC_DMCR_RA_BIT) | ((SDRAM_COL-8)<<EMC_DMCR_CA_BIT) | (SDRAM_BANK4<<EMC_DMCR_BA_BIT) | (SDRAM_BW16<<EMC_DMCR_BW_BIT) | EMC_DMCR_EPIN | cas_latency_dmcr[((SDRAM_CASL == 3) ? 1 : 0)]
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// SDRAM timimg
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ns = 1000000000 / mem_clk
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tmp = SDRAM_TRAS / ns
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if tmp < 4:
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tmp = 4
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if tmp > 11:
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tmp = 11
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dmcr |= ((tmp-4) << EMC_DMCR_TRAS_BIT)
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tmp = SDRAM_RCD/ns
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if tmp > 3:
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tmp = 3
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dmcr |= (tmp << EMC_DMCR_RCD_BIT)
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tmp = SDRAM_TPC/ns
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if tmp > 7:
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tmp = 7
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dmcr |= (tmp << EMC_DMCR_TPC_BIT)
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tmp = SDRAM_TRWL/ns
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if tmp > 3:
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tmp = 3
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dmcr |= (tmp << EMC_DMCR_TRWL_BIT)
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tmp = (SDRAM_TRAS + SDRAM_TPC)/ns
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if tmp > 14:
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tmp = 14
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dmcr |= (((tmp + 1) >> 1) << EMC_DMCR_TRC_BIT)
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// SDRAM mode value
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sdmode = EMC_SDMR_BT_SEQ | EMC_SDMR_OM_NORMAL | EMC_SDMR_BL_4 | cas_latency_sdmr[((SDRAM_CASL == 3) ? 1 : 0)];
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// Stage 1. Precharge all banks by writing SDMR with DMCR.MRSET=0
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EMC_DMCR = dmcr
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REG8(EMC_SDMR0|sdmode) = 0
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// Wait for precharge, > 200us
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tmp = (cpu_clk / 1000000) * 1000
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volatile unsigned t = tmp
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while t--:
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// Stage 2. Enable auto-refresh
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EMC_DMCR = dmcr | EMC_DMCR_RFSH
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tmp = SDRAM_TREF/ns
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tmp = tmp/64 + 1
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if tmp > 0xff:
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tmp = 0xff
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EMC_RTCOR = tmp
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EMC_RTCNT = 0
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// Divisor is 64, CKO/64
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EMC_RTCSR = EMC_RTCSR_CKS_64
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// Wait for number of auto-refresh cycles
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tmp = (cpu_clk / 1000000) * 1000
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t = tmp
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while t--:
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// Stage 3. Mode Register Set
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EMC_DMCR = dmcr0 | EMC_DMCR_RFSH | EMC_DMCR_MRSET
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REG8(EMC_SDMR0|sdmode) = 0
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// Set back to basic DMCR value
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EMC_DMCR = dmcr | EMC_DMCR_RFSH | EMC_DMCR_MRSET
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// everything is ok now: return to boot loader to load stage 2.
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