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components/74x1g04_6.lib: add single inverter; update HIERARCHY

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Werner Almesberger 2016-09-21 00:52:25 -03:00
parent 985ccbbe3c
commit c5450a1277
5 changed files with 38 additions and 0 deletions
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1
AUTHORS
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@ -41,6 +41,7 @@ Werner Almesberger <werner@almesberger.net>
components/8_10-card.lib
components/vga.lib
components/74x1g04_6.lib
components/74x1g08_5.lib (based on 74x1g00_5.lib)
components/74x1g08_6.lib (based on 74x1g00_5.lib)
components/74x1g07_5.lib

7
components/74x1g04_6.dcm Normal file
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@ -0,0 +1,7 @@
EESchema-DOCLIB Version 2.0
#
$CMP 74X1G04_6
D Single inverter in 6 pin package.
$ENDCMP
#
#End Doc Library

25
components/74x1g04_6.lib Normal file
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@ -0,0 +1,25 @@
EESchema-LIBRARY Version 2.3
#encoding utf-8
#
# 74X1G04_6
#
DEF 74X1G04_6 U 0 0 Y Y 1 F N
F0 "U" -200 200 60 H V C CNN
F1 "74X1G04_6" 100 -150 60 H V L CNN
F2 "" -150 175 60 H I C CNN
F3 "" -150 175 60 H I C CNN
DRAW
C 75 0 25 0 1 0 N
P 2 0 1 0 0 -50 0 -35 N
P 2 0 1 0 0 50 0 35 N
P 4 0 1 0 -100 -100 -100 100 50 0 -100 -100 N
X NC 1 300 150 200 L 50 40 1 1 N N
X A 2 -300 0 200 R 50 50 1 1 I
X GND 3 0 -250 200 U 50 40 1 1 W
X Y 4 300 0 200 L 50 50 1 1 O
X NC 5 300 100 200 L 50 40 1 1 N N
X VCC 6 0 250 200 D 50 40 1 1 W
ENDDRAW
ENDDEF
#
#End Library

4
components/HIERARCHY
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@ -16,15 +16,19 @@ Passive
Logic
Single
74x1g00_5
74x1g04_6
74x1g07_4
74x1g07_5
74x1g07_6
74x1g07_6
74x1g08_5
74x1g08_6
74x1g32_6
74x1g32_6-LARGE
74x1g125
Dual
74x2g07_6
74x2g07_6-LARGE
74x2g126
Shift
74x595

1
components/components.pro
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@ -170,3 +170,4 @@ LibName98=./tps6102x
LibName99=./gencon
LibName100=./74x2g07_6
LibName101=./74x1g32_6
LibName102=./74x1g04_6