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dvi-recept-ra.fpd: added DVI-RECEPT-RA
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Adam Wang
parent
2594403a96
commit
c87046103a
@ -77,6 +77,14 @@ F: do-214
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# http://www.fairchildsemi.com/dwg/DO/DO214AC.pdf
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#
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# CONN RECEPT ANALOG DIGITAL DVI RIGHT ANGLE
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F: dvi-recept-ra
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#
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# - DVI-RECEPT-RA, package drawing, land pattern
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# for example MOLEX 74320-1004
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# http://www.molex.com/pdm_docs/sd/743201004_sd.pdf
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#
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# EUS (R-PDSS-T6)
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F: eus
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#
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181
modules/dvi-recept-ra.fpd
Normal file
181
modules/dvi-recept-ra.fpd
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@ -0,0 +1,181 @@
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/* MACHINE-GENERATED ! */
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frame Cpins {
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table
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{ n, dx, dy }
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{ 1, -1, 1 }
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{ 2, 1, 1 }
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{ 3, -1, -1 }
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{ 4, 1, -1 }
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{ 5, 0, 2 }
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{ 5, 0, -2 }
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__0: vec @(dx*Cpitch/2, dy*Cpitch/2)
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__1: vec .(Cr/2, Cr/2)
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__2: vec __0(-Cr/2, -Cr/2)
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hole . __1
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__3: vec __0(factor*Cr/2, -factor*Cr/2)
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__4: vec __0(-factor*Cr/2, factor*Cr/2)
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rpad "C$n" . __3
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}
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frame shield {
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table
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{ n, dx }
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{ 25, -1 }
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{ 26, 1 }
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__0: vec @(dx*shieldx/2, 0mm)
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__1: vec .(shr/2, shr/2)
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__2: vec __0(-shr/2, -shr/2)
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hole . __1
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__3: vec __0(factor*shr/2, -factor*shr/2)
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__4: vec __0(-factor*shr/2, factor*shr/2)
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rpad "$n" . __3
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}
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frame ckt17pins {
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set n = i+17
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__0: vec @(i*cktpitch, 0mm)
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__1: vec .(cktr/2, cktr/2)
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__2: vec __0(-cktr/2, -cktr/2)
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hole . __1
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__3: vec __0(-factor*cktr/2, factor*cktr/2)
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__4: vec __0(factor*cktr/2, -factor*cktr/2)
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rpad "$n" __3 .
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}
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frame ckt9pins {
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set n = i+9
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__0: vec @(i*cktpitch, 0mm)
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__1: vec .(cktr/2, cktr/2)
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__2: vec __0(-cktr/2, -cktr/2)
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hole . __1
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__3: vec __0(-factor*cktr/2, factor*cktr/2)
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__4: vec __0(factor*cktr/2, -factor*cktr/2)
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rpad "$n" __3 .
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}
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frame ckt1pins {
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set n = i+1
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__0: vec @(i*cktpitch, 0mm)
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__1: vec .(cktr/2, cktr/2)
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__2: vec __0(-cktr/2, -cktr/2)
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hole . __1
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__3: vec __0(-factor*cktr/2, factor*cktr/2)
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__4: vec __0(factor*cktr/2, -factor*cktr/2)
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rpad "$n" __3 .
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}
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frame ckt {
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loop i = 0, 7
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__0: vec @(0mm, -ckt1to17y/2)
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frame ckt9pins .
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__1: vec .(0mm, -ckt1to17y/2)
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frame ckt17pins .
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__2: vec .(i*cktpitch, 0mm)
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frame ckt1pins @
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}
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frame npth {
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table
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{ dx }
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{ -1 }
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{ 1 }
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__0: vec @(dx*npthx/2, 0mm)
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__1: vec .(-npthr/2, npthr/2)
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__2: vec __0(npthr/2, -npthr/2)
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hole __1 .
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}
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frame outline {
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__0: vec @(-L/2, -(npth2edgey+frontmetaly))
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__1: vec .(L, PCBy+frontmetaly)
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rect __0 . w
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__2: vec .(0mm, -PCBy)
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__3: vec __0(0mm, frontmetaly)
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line . __2 w
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__4: vec @(0mm, -(npth2edgey+frontmetaly))
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__5: vec .(0mm, -face2outlety)
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__6: vec .(-face2outletx/2, 0mm)
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__7: vec __4(face2outletx/2, 0mm)
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rect __6 . w
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}
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package "DVI-RECEPT-RA"
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unit mm
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set npthx = 19.05mm
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set npthr = 1.93mm
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set npth2edgey = 1.93mm
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set shr = 1.93mm
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set ckt1to17y = 3.81mm
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set ckt17y = 3.3mm
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set ckt1toPCBedgey = 9.63mm
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set cktpitch = 1.91mm
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set cktr = 0.86mm
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set face2outlety = 6.5mm
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set face2outletx = 24.03mm
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set factor = 1.6
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set shieldx = 30.73mm
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set C4y = 3.94mm
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set C5y = 2.67mm
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set Cpitch = 2.54mm
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set Cr = 0.66mm
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set L = 36.83mm
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set PCBy = 10.95mm
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set frontmetaly = ckt1toPCBedgey-ckt1to17y-ckt17y-npth2edgey
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set w = 5mil
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__0: vec @(-npthx/2, ckt17y+ckt1to17y)
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frame ckt .
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__1: vec @(0mm, ckt17y)
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frame shield .
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__2: vec @(npthx/2-Cpitch/2, C4y+Cpitch/2)
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frame Cpins .
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frame npth @
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frame outline @
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meas npth.__0 >> npth.__0 -(npthr/2+0.5mm)
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meas __0 >> ckt1pins.__0 factor*cktr/2+0.5mm
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measy shield.__0 << npth.__0 shieldx-factor*shr/2-0.5mm
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measy shield.__0 >> __0 factor*shr+0.7mm
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measx Cpins.__0 -> Cpins.__0 -(Cpitch-Cr/2)
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measx Cpins.__0 >> Cpins.__0 -Cpitch
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meas Cpins.__0 >> Cpins.__0 -Cpitch
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measy Cpins.__0 << npth.__0 -Cpitch/2
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measy Cpins.__0 -> Cpins.__0
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meas ckt.__1 -> ckt.__2 -(factor*cktr/2+0.5mm)
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measx outline.__0 >> outline.__1 PCBy+frontmetaly+1.5mm
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measy outline.__3 >> outline.__1 2.2mm
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meas shield.__0 >> shield.__0 6.5mm
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measy outline.__3 -> npth.__0 0.8mm
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measy outline.__0 >> __0 1.5mm
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measx outline.__6 >> outline.__7 -0.8mm
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measy outline.__6 >> outline.__4 0.8mm
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measy outline.__6 >> outline.__1 (L-face2outletx)/2+3mm
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measy outline.__0 -> npth.__0 -factor*shr
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