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modules/lga.fpd: add LGA-20-3x4.5-BMX055
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@ -425,6 +425,7 @@ Quad
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LGA
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LGA-16-3x3
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LGA-8-2.5x2.5-BME280
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LGA-20-3x4.5-BMX055
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QFN
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QFN16-LFCSP_LQ
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QFN28-Atmel
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@ -6,15 +6,15 @@ frame piny {
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{ 0, i*f+a }
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{ 1, pins-a-i*f-nx+1 }
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__0: vec @(dx*(py/2+pe), px/2)
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__1: vec @(-dx*py/2, -px/2)
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__0: vec @(dx*(pyy/2+pe), pyx/2)
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__1: vec @(-dx*pyy/2, -pyx/2)
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pad "$name" . __0
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}
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frame pinsy {
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set y = e*(i-(ny-1)/2)
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set x = sx/2-py/2-b
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set x = sx/2-pyy/2-b
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table
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{ dx, f, a }
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@ -33,8 +33,8 @@ frame pinx {
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{ 0, i*f+a }
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{ 1, a+(nx-i-1)*f }
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__0: vec @(px/2, -dy*py/2)
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__1: vec @(-px/2, dy*py/2)
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__0: vec @(pxx/2, -dy*pxy/2)
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__1: vec @(-pxx/2, dy*pxy/2)
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__2: vec .(0mm, dy*pe)
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pad "$name" . __0
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}
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@ -57,7 +57,7 @@ frame outline {
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frame pinsx {
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set x = e*(i-(nx-1)/2)
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set y = sy/2-py/2-b
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set y = sy/2-pxy/2-b
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table
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{ dy, f, a }
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@ -74,9 +74,10 @@ package "LGA-$pins-${sizex}x${sizey}${variant}"
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unit mm
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table
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{ variant, nx, ny, sx, sy, e, b, px, py, pe, cw }
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{ "", 3, 5, 3mm, 3mm, 0.5mm, 0.1mm, 0.25mm, 0.35mm, 0.2mm, 0 }
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{ "-BME280", 0, 4, 2.5mm, 2.5mm, 0.65mm, 0.125mm, 0.35mm, 0.35mm, 0.15mm, 1 }
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{ variant, nx, ny, sx, sy, e, b, pxx, pxy, pyx, pyy, pe, cw }
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{ "", 3, 5, 3mm, 3mm, 0.5mm, 0.1mm, 0.25mm, 0.35mm, pxx, pxy, 0.2mm, 0 }
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{ "-BME280", 0, 4, 2.5mm, 2.5mm, 0.65mm, 0.125mm, 0.35mm, 0.35mm, pxx, pxy, 0.15mm, 1 }
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{ "-BMX055", 3, 7, 3mm, 4.5mm, 0.5mm, 0.1mm, 0.25mm, 0.375mm, pxx, 0.475mm, 0.2mm, 1 }
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set pins = 2*(nx+ny)
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@ -94,7 +95,7 @@ frame outline @
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measx outline.__2 >> outline.__0 -1.5mm
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measy outline.__2 >> outline.__0 1.5mm
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measx pinsx.__0 -> pinsx.__0 -1.5mm
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measx pinx.__2 -> pinx.__0 py+0.5mm
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measx pinx.__2 -> pinx.__0 pxy+0.5mm
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measy pinx.__1 -> pinx.__0 0.2mm
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measy pinx.__2 -> pinx.__1 0.2mm
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measy outline.__3 >> outline.__5 1.5mm
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@ -104,3 +105,4 @@ measx piny.__0 -> piny.__1
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measx piny.__1 -> piny.__1 0.8mm
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measx piny.__0 -> piny.__0 1mm
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measy pinsy.__0 -> pinsy.__0 1mm
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measy pinx.__0 -> pinx.__0 2.2mm
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