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added SOIC footprints: 8, 14 and 16 pins.
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18
modules/INFO
18
modules/INFO
@ -144,3 +144,21 @@ F: mdip
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#
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# http://www.fairchildsemi.com/dwg/N0/N08H.pdf
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# SOIC
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F: soic
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#
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# From TI:
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#
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# - the SN75HVD12DR data sheet
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# http://www.ti.com/lit/ds/symlink/sn75hvd12.pdf
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#
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# Package Drawing:
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#
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# - D(JEDEC)
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# - R-PDSO-G8
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# http://www-s.ti.com/sc/psheets/msoi002j/msoi002j.pdf
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# - R-PDSO-G14
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# http://www-s.ti.com/sc/psheets/mpds177g/mpds177g.pdf
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# - R-PDSO-G16
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# http://www-s.ti.com/sc/psheets/mpds178g/mpds178g.pdf
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79
modules/soic.fpd
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79
modules/soic.fpd
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@ -0,0 +1,79 @@
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/* MACHINE-GENERATED ! */
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frame pin {
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__0: vec @(D/2, C/2)
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__1: vec @(-D/2, -C/2)
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pad "$n" . __0
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}
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frame pins_top {
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set n = N-i
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__0: vec @(x, 0mm)
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frame pin .
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}
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frame pins_bottom {
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set n = i+1
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__0: vec @(x, 0mm)
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frame pin .
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}
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frame pins {
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set y = (A+B)/4
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set x = (i-(N/2-1)/2)*Pitch
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loop i = 0, N/2-1
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__0: vec @(0mm, y)
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frame pins_top .
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__1: vec @(0mm, -y)
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frame pins_bottom .
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}
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frame marker {
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set r = ((N/2-1)*Pitch-x)/2-w
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__0: vec @(-x/2-D+w, -(A-C)/2)
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__1: vec .(-r/3, 0mm)
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circ __0 . w
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}
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frame outline {
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set w = 5mil
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set x = H
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set y = A+2*w
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__0: vec @(x/2, y/2)
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__1: vec @(-x/2, -y/2)
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rect . __0 w
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frame marker @
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}
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package "$name-$N"
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unit mm
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set Pitch = 1.27mm
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set D = 0.6mm
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table
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{ name, N, A, B, C, H }
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{ "SOIC", 8, 6.8mm, 2.8mm, 2mm, 4.9mm }
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{ "SOIC", 14, 6.8mm, 2.8mm, 2mm, 8.65mm }
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{ "SOIC", 16, 6.8mm, 2.8mm, 2mm, 9.9mm }
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frame outline @
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frame pins @
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measy pin.__1 -> pin.__0 1.5mm
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measy pin.__1 >> pin.__0 -H-2mm
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measy pin.__0 >> pin.__1 -H
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measx pin.__1 -> pin.__0 -1mm
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measx pins_top.__0 -> pins_top.__0 -2mm
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measy pins.__0 << pins_bottom.__0 -2mm
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measy outline.__0 >> outline.__1 -H-C
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measx outline.__1 >> outline.__0 8mm
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