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nn-usb-fpga/UART/logic/build/project.pcf

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//! **************************************************************************
// Written by: Map K.39 on Thu Nov 11 14:38:06 2010
//! **************************************************************************
SCHEMATIC START;
COMP "addr<2>" LOCATE = SITE "P79" LEVEL 1;
COMP "clk" LOCATE = SITE "P38" LEVEL 1;
COMP "sram_data<0>" LOCATE = SITE "P16" LEVEL 1;
COMP "sram_data<1>" LOCATE = SITE "P15" LEVEL 1;
COMP "sram_data<2>" LOCATE = SITE "P12" LEVEL 1;
COMP "sram_data<3>" LOCATE = SITE "P11" LEVEL 1;
COMP "sram_data<4>" LOCATE = SITE "P10" LEVEL 1;
COMP "led" LOCATE = SITE "P44" LEVEL 1;
COMP "sram_data<5>" LOCATE = SITE "P9" LEVEL 1;
COMP "sram_data<6>" LOCATE = SITE "P5" LEVEL 1;
COMP "RxD" LOCATE = SITE "P68" LEVEL 1;
COMP "sram_data<7>" LOCATE = SITE "P4" LEVEL 1;
COMP "TxD" LOCATE = SITE "P67" LEVEL 1;
COMP "ncs" LOCATE = SITE "P69" LEVEL 1;
COMP "noe" LOCATE = SITE "P86" LEVEL 1;
COMP "irq_pin" LOCATE = SITE "P71" LEVEL 1;
COMP "nwe" LOCATE = SITE "P88" LEVEL 1;
COMP "reset" LOCATE = SITE "P30" LEVEL 1;
COMP "addr<0>" LOCATE = SITE "P84" LEVEL 1;
COMP "addr<1>" LOCATE = SITE "P83" LEVEL 1;
NET "clk_BUFGP/IBUFG" BEL "clk_BUFGP/BUFG.GCLKMUX" USELOCALCONNECT;
SCHEMATIC END;