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Fixing Makefile errors

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This commit is contained in:
Carlos Camargo
2010-05-12 10:06:23 -05:00
parent 7bc5ac45ea
commit 47b7172e98
10 changed files with 25 additions and 42 deletions
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4
Examples/blink/logic/Makefile
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@@ -74,7 +74,7 @@ $(DESIGN).bit: build/project_r.ncd build/project_r.twr
@mv -f build/project_r.bit $@
build/project_r.v: build/project_r.ncd
cd build && netgen -sim -ofmt vhdl project_r.ncd -pcf project.pcf && ngd2ver projecsimulationt.ngd -w project.v
cd build && ngd2ver project.ngd -w project.v
modelsim:
cd simulation; $(SIM_CMD) -do $(DESIGN)_TB.do
@@ -83,7 +83,7 @@ timesim: build/project_r.v
cd simulation; $(SIM_CMD) -do $(DESIGN)_TIMING_TB.do
iversim:
$(IVERILOG) -o simulation/$(DESIGN)_TB.vvp $(VINCDIR) $(SRC) $(SIM_SRC) -s $(DESIGN)_TB_v
$(IVERILOG) -o simulation/$(DESIGN)_TB.vvp $(VINCDIR) $(SRC) $(SIM_SRC) -s $(DESIGN)_TB
vvp simulation/$(DESIGN)_TB.vvp; mv $(DESIGN)_TB.vcd simulation/
gtkwave simulation/$(DESIGN)_TB.vcd&

2
Examples/blink/logic/blink_TB.v
View File

@@ -1,6 +1,6 @@
`timescale 1ns / 1ps
module blink_TB_v;
module blink_TB;
reg clk;
reg reset;