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Fixing Makefile errors

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This commit is contained in:
Carlos Camargo
2010-05-12 10:06:23 -05:00
parent 7bc5ac45ea
commit 47b7172e98
10 changed files with 25 additions and 42 deletions
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29
Examples/sram/logic/simulation/transcript
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@@ -8,49 +8,26 @@
# // OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS
# // AND IS SUBJECT TO LICENSE TERMS.
# //
# do sram_bus_TIMING_TB.do
# do sram_bus_TB.do
# ** Warning: (vlib-34) Library already exists at "work".
# Model Technology ModelSim SE vlog 6.0d Compiler 2005.04 Apr 25 2005
# -- Compiling module sram_bus
# -- Compiling module glbl
# -- Compiling module sram_bus_TB
# ** Warning: glbl.v(5): 'glbl' already exists.
# -- Compiling module glbl
#
# Top level modules:
# glbl
# sram_bus_TB
# glbl
# vsim -L simprims_ver -L unisims_ver -L xilinxcorelib_ver -t 1ps sram_bus_TB glbl
# Loading work.sram_bus_TB
# Loading work.sram_bus
# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_ONE
# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_ZERO
# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_FF
# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_SFF
# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_MUX2
# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_XOR2
# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_LUT2
# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_BUF
# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_LUT3
# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_INV
# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_RAMB16_S2
# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_BPAD
# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_IPAD
# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_OPAD
# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_CKBUF
# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_OBUFT
# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_OBUF
# Loading /opt/cad/modeltech/xilinx/verilog/unisims_ver.RAMB16_S2
# Loading work.glbl
# ** Warning: (vsim-3017) ../sram_bus_TB.v(21): [TFMPC] - Too few port connections. Expected 8, found 7.
# Region: /sram_bus_TB/uut
# ** Warning: (vsim-3015) ../sram_bus_TB.v(21): [PCDPC] - Port size (8 or 8) does not match connection size (1) for port 'sram_data'.
# Region: /sram_bus_TB/uut
# ** Warning: (vsim-3722) ../sram_bus_TB.v(21): [TFMPC] - Missing connection for port 'led'.
# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.ffsrce
# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.sffsrce
# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.mux
# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.x_lut2_mux4
# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.x_lut3_mux4
# .main_pane.mdi.interior.cs.vm.paneset.cli_0.wf.clip.cs
# .main_pane.workspace
# .main_pane.signals.interior.cs