Fixing Makefile errors

Examples/sram/logic/simulation/work/_info

@@ -11,24 +11,27 @@ L0 5
 OE;L;6.0d;29
 r1
 31
+o+libext+.v
 vsram_bus
-IhWan4YkPClmK5z;GkOZUS2
-V7bnNHP1kz?3UaZfjPj4WE1
-w1273543976
-F../build/project.v
-L0 37
+I4L5C3LJ<U_bBN0U__mYo>0
+V7R>S0^PdJz?6eY;E[l1^E2
+w1273543761
+F../sram_bus.v
+L0 2
 OE;L;6.0d;29
 r1
 31
+o+libext+.v
 vsram_bus_TB
 IeNSImUgW[X4l`QoUVUKI`3
 V<VFiY^801Z<UUJ?^z?JM20
-w1273543928
+w1273676679
 F../sram_bus_TB.v
 L0 3
 OE;L;6.0d;29
 r1
 31
+o+libext+.v
 nsram_bus_@t@b
 vsram_bus_TB_v
 IA=m;kT@<eh:`ekMlOPXX@0

Examples/sram/logic/simulation/work/sram_bus/_primary.vhd

@@ -1,14 +1,17 @@
 library verilog;
 use verilog.vl_types.all;
 entity sram_bus is
+    generic(
+        B               : integer := 7
+    );
     port(
         clk             : in     vl_logic;
-        reset           : in     vl_logic;
+        sram_data       : inout  vl_logic_vector;
+        addr            : in     vl_logic_vector(12 downto 0);
+        nwe             : in     vl_logic;
         ncs             : in     vl_logic;
         noe             : in     vl_logic;
-        nwe             : in     vl_logic;
-        led             : out    vl_logic;
-        sram_data       : inout  vl_logic_vector(7 downto 0);
-        addr            : in     vl_logic_vector(12 downto 0)
+        reset           : in     vl_logic;
+        led             : out    vl_logic
     );
 end sram_bus;