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Adding diagrams to DOCS and fixing someting source code.
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@ -2,7 +2,7 @@
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ADCw::ADCw()
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ADCw::ADCw()
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{
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{
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BUFFER_OFFSET = 9;
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BUFFER_OFFSET = 8; //Ignore first 16 samples
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ADC_SPI_CLKDIV=ADC_SPI_CLKDIV_MAX; //Set clock to minimum speed
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ADC_SPI_CLKDIV=ADC_SPI_CLKDIV_MAX; //Set clock to minimum speed
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BUFFER_LEN=16;
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BUFFER_LEN=16;
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MUX_CHANNELS =0;
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MUX_CHANNELS =0;
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@ -65,7 +65,7 @@ JZ_REG* ADCw::takeSamplesADC(int CHANNEL)
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void ADCw::adcConfig(uchar CMD)
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void ADCw::adcConfig(uchar CMD)
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{
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{
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ADCBuffer[0] = (((MUX_CHANNELS<<6) + CMD)<<24) + \
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ADCBuffer[0] = (((MUX_CHANNELS<<6) + CMD)<<24) + \
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((BUFFER_LEN+(BUFFER_OFFSET-1)*2) << 8) + \
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((BUFFER_LEN+BUFFER_OFFSET*2) << 8) + \
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(ADC_SPI_CLKDIV);
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(ADC_SPI_CLKDIV);
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while(adcCheckBufferFull()) usleep (10);
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while(adcCheckBufferFull()) usleep (10);
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}
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}
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@ -1,6 +1,6 @@
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#############################################################################
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#############################################################################
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# Makefile for building: ADC
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# Makefile for building: ADC
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# Generated by qmake (2.01a) (Qt 4.6.2) on: Mon Apr 12 21:21:04 2010
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# Generated by qmake (2.01a) (Qt 4.6.2) on: Wed Apr 14 21:04:10 2010
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# Project: ADC1.pro
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# Project: ADC1.pro
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# Template: app
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# Template: app
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# Command: /home/juan64bits/ebd/ECB/openwrt-xburst/build_dir/target-mipsel_uClibc-0.9.30.1/qt-everywhere-opensource-src-4.6.2/bin/qmake -spec ../../../../openwrt-xburst/build_dir/target-mipsel_uClibc-0.9.30.1/qt-everywhere-opensource-src-4.6.2/mkspecs/qws/linux-openwrt-g++ -unix -o Makefile ADC1.pro
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# Command: /home/juan64bits/ebd/ECB/openwrt-xburst/build_dir/target-mipsel_uClibc-0.9.30.1/qt-everywhere-opensource-src-4.6.2/bin/qmake -spec ../../../../openwrt-xburst/build_dir/target-mipsel_uClibc-0.9.30.1/qt-everywhere-opensource-src-4.6.2/mkspecs/qws/linux-openwrt-g++ -unix -o Makefile ADC1.pro
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@ -17,8 +17,7 @@ module ADC_peripheral( clk, reset, cs, ADC_EOC, ADC_CS, ADC_CSTART,
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wire [7:0] rdBus1;
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wire [7:0] rdBus1;
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reg [7:0] wrBus2;
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reg [7:0] wrBus2;
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reg [10:0] addr2;
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reg [10:0] addr2;
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reg we1=0;
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reg we1=0, we2=0;
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reg we2=0;
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wire we;
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wire we;
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//Control registers
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//Control registers
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@ -40,12 +39,13 @@ module ADC_peripheral( clk, reset, cs, ADC_EOC, ADC_CS, ADC_CSTART,
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//TEMPS
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//TEMPS
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reg [9:0] SIZEB1=0; // Temporal for buffer size
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reg [9:0] SIZEB1=0; // Temporal for buffer size
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reg [9:0] SIZEB2=0; // Temporal for buffer size
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reg [9:0] SIZEB2=0; // Temporal for buffer size
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wire[9:0] subSIZEB; // Temporal for subtraction SIZEB1-SIZEB2
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reg [2:0] CMD_OFFSET=0; // Channel offset counter MOD8
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reg [2:0] CMD_OFFSET=0; // Channel offset counter MOD8
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wire[2:0] CMD_OFFSETt; // Channel offset to use
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wire[2:0] CMD_OFFSETt; // Channel offset to use
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wire[3:0] CMD_ADCt; // Temporal for channel offset
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wire[3:0] CMD_ADCt; // Temporal for channel offset
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assign ADC_CSTART = 1'b1;
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assign ADC_CSTART = 1'b1;
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// Dual-port RAM instatiation
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// Dual-port RAM instatiation
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RAMB16_S9_S9 ba0(
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RAMB16_S9_S9 ba0(
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.DOA(rdBus1), // Port A 8-bit Data Output
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.DOA(rdBus1), // Port A 8-bit Data Output
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@ -216,7 +216,7 @@ module ADC_peripheral( clk, reset, cs, ADC_EOC, ADC_CS, ADC_CSTART,
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4: begin loadB <= 0; initB<=0; w_st0<= 0; end
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4: begin loadB <= 0; initB<=0; w_st0<= 0; end
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endcase
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endcase
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end
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end
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// Reception Buffer
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// Reception Buffer
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always @(posedge clk)
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always @(posedge clk)
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if(reset)
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if(reset)
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@ -245,14 +245,14 @@ module ADC_peripheral( clk, reset, cs, ADC_EOC, ADC_CS, ADC_CSTART,
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2: begin
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2: begin
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//Write data on BRAM (LOW)
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//Write data on BRAM (LOW)
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wrBus2[7:0] <= out_buffer[7:0];
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wrBus2[7:0] <= out_buffer[7:0];
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addr2 <= 4+2*(SIZEB1-SIZEB2);
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addr2 <= {subSIZEB,1'b0};
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we2 <= 1; w_st2 <= 3;
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we2 <= 1; w_st2 <= 3;
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end
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end
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3: begin we2 <= 0; w_st2 <= 4; end
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3: begin we2 <= 0; w_st2 <= 4; end
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4: begin
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4: begin
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//Write data on BRAM (HI)
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//Write data on BRAM (HI)
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wrBus2[7:0] <= {CMD_OFFSETt,2'b00,out_buffer[9:8]};
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wrBus2[7:0] <= out_buffer[9:8];
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addr2 <= 5+2*(SIZEB1-SIZEB2);
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addr2 <= {subSIZEB,1'b1};
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we2 <= 1; w_st2 <= 5;
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we2 <= 1; w_st2 <= 5;
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end
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end
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5: begin
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5: begin
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@ -261,6 +261,8 @@ module ADC_peripheral( clk, reset, cs, ADC_EOC, ADC_CS, ADC_CSTART,
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endcase
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endcase
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end
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end
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assign subSIZEB = SIZEB1-SIZEB2;
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// ADC channel offset, counter MOD8
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// ADC channel offset, counter MOD8
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always @(posedge clk)
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always @(posedge clk)
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if(fullB | reset)
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if(fullB | reset)
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@ -1 +0,0 @@
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Juan64Bits ,juan64bits,Maximus,12.04.2010 22:34,file:///home/juan64bits/.openoffice.org/3;
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docs/wiki/ADC_BUFFER.dia
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docs/wiki/ADC_BUFFER.dia
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docs/wiki/ADC_BUFFER.dia~
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docs/wiki/ADC_BUFFER.dia~
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docs/wiki/ADC_CONTROL.dia
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docs/wiki/ADC_CONTROL.dia
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docs/wiki/ADC_SPI_CTRL.dia
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docs/wiki/ADC_SPI_CTRL.dia
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docs/wiki/sw_hw_fpga_arch.odg
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docs/wiki/sw_hw_fpga_arch.odg
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