qi-hardware/nn-usb-fpga
1
0
Fork 0
mirror of git://projects.qi-hardware.com/nn-usb-fpga.git synced 2025-01-08 14:30:15 +02:00
Code

Adding ADC software example

Browse Source
This commit is contained in:
Juan64Bits 2010-04-02 23:30:52 -05:00
parent 4d27db9265
commit 68b6b9a51f
10 changed files with 582 additions and 49 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

79
Examples/ADC/logic/ADC.v
View File

@ -16,30 +16,27 @@ module ADC(clk, sram_data, addr, nwe, ncs, noe, reset, led, ADC_EOC,
// synchronize signals
reg sncs, snwe;
reg [10:0] buffer_addr;
wire [8:0] addr2;
reg [B:0] buffer_data;
// interfaz fpga signals
wire [10:0] addr;
// bram interfaz signals
reg we;
wire we2;
reg w_st=0;
reg [B:0] wrBus;
wire [B:0] rdBus;
wire [B:0] wrBus2;
wire [B:0] rdBus2;
// interfaz fpga signals
wire [10:0] addr;
reg [25:0] counter;
// Test : LED blinking
always @(posedge clk) begin
if (reset)
counter <= {25{1'b0}};
else
counter <= counter + 1;
led <=counter[25];
if (reset)
counter <= {25{1'b0}};
else
counter <= counter + 1;
led <=counter[25];
end
// interefaz signals assignments
@ -49,10 +46,10 @@ module ADC(clk, sram_data, addr, nwe, ncs, noe, reset, led, ADC_EOC,
// synchronize assignment
always @(negedge clk)
begin
sncs <= ncs;
snwe <= nwe;
buffer_data <= sram_data;
buffer_addr <= addr;
sncs <= ncs;
snwe <= nwe;
buffer_data <= sram_data;
buffer_addr <= addr;
end
// write access cpu to bram
@ -75,30 +72,34 @@ module ADC(clk, sram_data, addr, nwe, ncs, noe, reset, led, ADC_EOC,
endcase
end
// Dual-port RAM instatiation
RAMB16_S9_S9 ba0(
.DOA(rdBus), // Port A 8-bit Data Output
.DOB(rdBus2), // Port B 8-bit Data Output
.DOPA(), // Port A 1-bit Parity Output
.DOPB(), // Port B 1-bit Parity Output
.ADDRA(buffer_addr[10:0]), // Port A 11-bit Address Input
.ADDRB(addr2[8:0]), // Port B 11-bit Address Input
.CLKA(~clk), // Port A Clock
.CLKB(~clk), // Port B Clock
.DIA(wrBus), // Port A 8-bit Data Input
.DIB(wrBus2), // Port B 8-bit Data Input
.DIPA(1'b0), // Port A 1-bit parity Input
.DIPB(1'b0), // Port-B 1-bit parity Input
.ENA(1'b1), // Port A RAM Enable Input
.ENB(1'b1), // Port B RAM Enable Input
.SSRA(1'b0), // Port A Synchronous Set/Reset Input
.SSRB(1'b0), // Port B Synchronous Set/Reset Input
.WEA(we), // Port A Write Enable Input
.WEB(we2) ); // Port B Write Enable Input
// Peripherals control
wire [3:0] csN;
wire [7:0] rdBus0, rdBus1, rdBus2, rdBus3;
assign csN = buffer_addr[10]? (buffer_addr[9]? 4'b1000:
4'b0100)
: (buffer_addr[9]? 4'b0010:
4'b0001);
assign rdBus = buffer_addr[10]? (buffer_addr[9]? rdBus3:
rdBus2)
: (buffer_addr[9]? rdBus1:
rdBus0);
// Peripheral instantiation
ADC_peripheral P1( clk, reset, ADC_EOC, ADC_CS, ADC_CSTART,
ADC_SCLK, ADC_SDIN, ADC_SDOUT, we2,
rdBus2, wrBus2, addr2);
ADC_peripheral P1(
.clk(clk),
.reset(reset),
.cs(csN[0]),
.ADC_EOC(ADC_EOC),
.ADC_CS(ADC_CS),
.ADC_CSTART(ADC_CSTART),
.ADC_SCLK(ADC_SCLK),
.ADC_SDIN(ADC_SDIN),
.ADC_SDOUT(ADC_SDOUT),
.addr(buffer_addr[8:0]),
.rdBus(rdBus0),
.wrBus(wrBus),
.we(we));
endmodule

47
Examples/ADC/logic/ADC_peripheral.v
View File

@ -1,18 +1,21 @@
`timescale 1ns / 1ps
module ADC_peripheral( clk, reset, ADC_EOC, ADC_CS, ADC_CSTART,
ADC_SCLK, ADC_SDIN, ADC_SDOUT, we2,
rdBus2, wrBus2, addr2);
module ADC_peripheral( clk, reset, cs, ADC_EOC, ADC_CS, ADC_CSTART,
ADC_SCLK, ADC_SDIN, ADC_SDOUT,
addr, rdBus, wrBus, we);
input clk, reset, ADC_EOC;
input [7:0] rdBus2;
output we2, ADC_CS, ADC_CSTART, ADC_SCLK;
output [7:0] wrBus2;
output [8:0] addr2;
input clk, reset, ADC_EOC, cs, we;
input [8:0] addr;
input [7:0] wrBus;
output ADC_CS, ADC_CSTART, ADC_SCLK;
output [7:0] rdBus;
inout ADC_SDIN, ADC_SDOUT;
reg we2=0, nSample=0;
wire [7:0] rdBus2;
reg [7:0] wrBus2;
reg [8:0] addr2;
wire we1;
reg we2=0, nSample=0;
reg [7:0] auto_count=0;
reg [4:0] w_st2=0;
reg [3:0] SPI_in_data=0;
@ -22,8 +25,31 @@ module ADC_peripheral( clk, reset, ADC_EOC, ADC_CS, ADC_CSTART,
reg [7:0] buffer_rd1;
reg [3:0] ADC_cmd;
assign we1 = we & cs;
assign ADC_CSTART = 1'b1;
// Dual-port RAM instatiation
RAMB16_S9_S9 ba0(
.DOA(rdBus), // Port A 8-bit Data Output
.DOB(rdBus2), // Port B 8-bit Data Output
.DOPA(), // Port A 1-bit Parity Output
.DOPB(), // Port B 1-bit Parity Output
.ADDRA(addr[8:0]), // Port A 11-bit Address Input
.ADDRB(addr2[8:0]), // Port B 11-bit Address Input
.CLKA(~clk), // Port A Clock
.CLKB(~clk), // Port B Clock
.DIA(wrBus), // Port A 8-bit Data Input
.DIB(wrBus2), // Port B 8-bit Data Input
.DIPA(1'b0), // Port A 1-bit parity Input
.DIPB(1'b0), // Port-B 1-bit parity Input
.ENA(1'b1), // Port A RAM Enable Input
.ENB(1'b1), // Port B RAM Enable Input
.SSRA(1'b0), // Port A Synchronous Set/Reset Input
.SSRB(1'b0), // Port B Synchronous Set/Reset Input
.WEA(we1), // Port A Write Enable Input
.WEB(we2) ); // Port B Write Enable Input
// SPI comunication module instantiation
reg ADC_SCLK_buffer = 0;
reg ADC_SDIN_buffer = 0;
@ -157,5 +183,6 @@ module ADC_peripheral( clk, reset, ADC_EOC, ADC_CS, ADC_CSTART,
//Sent clock divider for speed on SPI comunication
10: begin clkdiv = rdBus2; w_st2 <= 0; end
endcase
end
end
endmodule

36
Examples/ADC/src/Makefile Normal file
View File

@ -0,0 +1,36 @@
CC = mipsel-openwrt-linux-gcc
all: upload
DEBUG = -O3 -g0
COMMON_SOURCES = jz47xx_gpio.c jz47xx_mmap.c jz_adc_peripheral.c
H_SOURCES = jz47xx_gpio.h jz47xx_mmap.h jz_adc_peripheral.h
INCLUDE = -I.
WARNINGS= -Wcast-align -Wpacked -Wpadded -Wall
CCFLAGS = ${INCLUDE} ${DEBUG} ${WARNINGS}
LDFLAGS =
COMMON_OBJECTS = $(COMMON_SOURCES:.c=.o)
NANO_IP = 192.168.254.101
jz_test_adc: $(COMMON_OBJECTS)
$(CC) $(LDFLAGS) $(COMMON_OBJECTS) jz_test_adc.c -o jz_test_adc
.c.o:
$(CC) -c $(CCFLAGS) $< -o $@
upload: jz_test_adc
scp jz_test_adc root@$(NANO_IP):/root/
clean:
rm -f *.o jz_test_adc ${EXEC} *~
indent:
indent -bad -bap -nbc -bl -nce -i2 --no-tabs --line-length120 $(COMMON_SOURCES) $(H_SOURCES)

108
Examples/ADC/src/jz47xx_gpio.c Normal file
View File

@ -0,0 +1,108 @@
/*
JZ47xx GPIO at userspace
Copyright (C) 2010 Andres Calderon andres.calderon@emqbit.com
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */
#include <stdio.h>
#include <stdlib.h>
#include <unistd.h>
#include <jz47xx_gpio.h>
#include <jz47xx_mmap.h>
#define JZ_GPIO_BASE 0x10010000
void
jz_gpio_as_output (JZ_PIO * pio, unsigned int o)
{
pio->PXFUNC = (1 << (o));
pio->PXSELC = (1 << (o));
pio->PXDIRS = (1 << (o));
}
void
jz_gpio_as_input (JZ_PIO * pio, unsigned int o)
{
pio->PXFUNC = (1 << (o));
pio->PXSELC = (1 << (o));
pio->PXDIRC = (1 << (o));
}
void
jz_gpio_set_pin (JZ_PIO * pio, unsigned int o)
{
pio->PXDATS = (1 << (o));
}
void
jz_gpio_clear_pin (JZ_PIO * pio, unsigned int o)
{
pio->PXDATC = (1 << (o));
}
void
jz_gpio_out (JZ_PIO * pio, unsigned int o, unsigned int val)
{
if (val == 0)
pio->PXDATC = (1 << (o));
else
pio->PXDATS = (1 << (o));
}
unsigned int
jz_gpio_get_pin (JZ_PIO * pio, unsigned int o)
{
return (pio->PXPIN & (1 << o)) ? 1 : 0;
}
int
jz_gpio_as_func (JZ_PIO * pio, unsigned int o, int func)
{
switch (func)
{
case 0:
pio->PXFUNS = (1 << o);
pio->PXTRGC = (1 << o);
pio->PXSELC = (1 << o);
return 1;
case 1:
pio->PXFUNS = (1 << o);
pio->PXTRGC = (1 << o);
pio->PXSELS = (1 << o);
return 1;
case 2:
pio->PXFUNS = (1 << o);
pio->PXTRGS = (1 << o);
pio->PXSELC = (1 << o);
return 1;
}
return 0;
}
JZ_PIO *
jz_gpio_map (int port)
{
JZ_PIO *pio;
pio = (JZ_PIO *) jz_mmap (JZ_GPIO_BASE);
pio = (JZ_PIO *) ((unsigned int) pio + port * 0x100);
return pio;
}

84
Examples/ADC/src/jz47xx_gpio.h Normal file
View File

@ -0,0 +1,84 @@
/*
JZ47xx GPIO at userspace
Copyright (C) 2010 Andres Calderon andres.calderon@emqbit.com
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */
#ifndef __jz47xx_gpio_h__
#define __jz47xx_gpio_h__
#define JZ_GPIO_PORT_A 0
#define JZ_GPIO_PORT_B 1
#define JZ_GPIO_PORT_C 2
#define JZ_GPIO_PORT_D 3
typedef volatile unsigned int JZ_REG; /* Hardware register definition */
typedef struct _JZ_PIO
{
JZ_REG PXPIN; /* PIN Level Register */
JZ_REG Reserved0;
JZ_REG Reserved1;
JZ_REG Reserved2;
JZ_REG PXDAT; /* Port Data Register */
JZ_REG PXDATS; /* Port Data Set Register */
JZ_REG PXDATC; /* Port Data Clear Register */
JZ_REG Reserved3;
JZ_REG PXIM; /* Interrupt Mask Register */
JZ_REG PXIMS; /* Interrupt Mask Set Reg */
JZ_REG PXIMC; /* Interrupt Mask Clear Reg */
JZ_REG Reserved4;
JZ_REG PXPE; /* Pull Enable Register */
JZ_REG PXPES; /* Pull Enable Set Reg. */
JZ_REG PXPEC; /* Pull Enable Clear Reg. */
JZ_REG Reserved5;
JZ_REG PXFUN; /* Function Register */
JZ_REG PXFUNS; /* Function Set Register */
JZ_REG PXFUNC; /* Function Clear Register */
JZ_REG Reserved6;
JZ_REG PXSEL; /* Select Register */
JZ_REG PXSELS; /* Select Set Register */
JZ_REG PXSELC; /* Select Clear Register */
JZ_REG Reserved7;
JZ_REG PXDIR; /* Direction Register */
JZ_REG PXDIRS; /* Direction Set Register */
JZ_REG PXDIRC; /* Direction Clear Register */
JZ_REG Reserved8;
JZ_REG PXTRG; /* Trigger Register */
JZ_REG PXTRGS; /* Trigger Set Register */
JZ_REG PXTRGC; /* Trigger Set Register */
JZ_REG Reserved9;
JZ_REG PXFLG; /* Port Flag Register */
JZ_REG PXFLGC; /* Port Flag clear Register */
} JZ_PIO, *PJZ_PIO;
void jz_gpio_as_output (JZ_PIO * pio, unsigned int o);
void jz_gpio_as_input (JZ_PIO * pio, unsigned int o);
void jz_gpio_set_pin (JZ_PIO * pio, unsigned int o);
void jz_gpio_clear_pin (JZ_PIO * pio, unsigned int o);
void jz_gpio_out (JZ_PIO * pio, unsigned int o, unsigned int val);
unsigned int jz_gpio_get_pin (JZ_PIO * pio, unsigned int o);
int jz_gpio_as_func (JZ_PIO * pio, unsigned int o, int func);
JZ_PIO *jz_gpio_map (int port);
#endif

39
Examples/ADC/src/jz47xx_mmap.c Normal file
View File

@ -0,0 +1,39 @@
/*
* JZ47xx GPIO lines
*
* Written 2010 by Andres Calderon andres.calderon@emqbit.com
*/
#include <stdio.h>
#include <sys/mman.h>
#include <fcntl.h>
#include <stdlib.h>
#include <termios.h>
#include <unistd.h>
#include <jz47xx_mmap.h>
void *
jz_mmap (off_t address)
{
int fd;
void *pio;
if ((fd = open ("/dev/mem", O_RDWR | O_SYNC)) == -1)
{
fprintf (stderr, "Cannot open /dev/mem.\n");
return 0;
}
pio = (void *) mmap (0, getpagesize (), PROT_READ | PROT_WRITE, MAP_SHARED, fd, address);
if (pio == (void *) -1)
{
fprintf (stderr, "Cannot mmap.\n");
return 0;
}
return pio;
}

14
Examples/ADC/src/jz47xx_mmap.h Normal file
View File

@ -0,0 +1,14 @@
/*
* JZ47xx GPIO lines
*
* Written 2010 by Andres Calderon andres.calderon@emqbit.com
*/
#ifndef __jz47xx_mmap_h__
#define __jz47xx_mmap_h__
#include <sys/mman.h>
void *jz_mmap (off_t address);
#endif

36
Examples/ADC/src/jz_adc_peripheral.c Normal file
View File

@ -0,0 +1,36 @@
/* ADC Peripheral.c
Copyright (C) 2010 Carlos Camargo cicamargoba@unal.edu.co
Andres Calderon andres.calderon@emqbit.com
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */
#include <stdio.h>
#include <unistd.h>
#include "jz_adc_peripheral.h"
void
jz_adc_config(JZ_REG * addr, uchar BUFFER, uchar CLK_DIV, uchar CMD)
{
addr[0] = (BUFFER << 16) + (CLK_DIV<<8) + CMD;
}
int
jz_adc_check_buffer(JZ_REG * addr)
{
return addr[0]&0x00FF0000;
}

78
Examples/ADC/src/jz_adc_peripheral.h Normal file
View File

@ -0,0 +1,78 @@
/* ADC Peripheral.h
Copyright (C) 2010 Carlos Camargo cicamargoba@unal.edu.co
Andres Calderon andres.calderon@emqbit.com
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */
#ifndef __adc_peropheral_h__
#define __adc_peropheral_h__
#include "jz47xx_gpio.h"
#define ADC_CMD_NONE 0x00 /* Nothing to do */
#define ADC_CMD_SET_SPI_CLKDIV 0x90 /* Set clock divider for ADC sclk */
#define ADC_CMD_SET_CHANNEL0 0x50 /* Set channel 0 */
#define ADC_CMD_READ_CHANNEL0 0x60 /* Read channel 0 */
#define ADC_CMD_SET_CHANNEL1 0x51 /* Set channel 1 */
#define ADC_CMD_READ_CHANNEL1 0x61 /* Read channel 1 */
#define ADC_CMD_SET_CHANNEL2 0x52 /* Set channel 2 */
#define ADC_CMD_READ_CHANNEL2 0x62 /* Read channel 2 */
#define ADC_CMD_SET_CHANNEL3 0x53 /* Set channel 3 */
#define ADC_CMD_READ_CHANNEL3 0x63 /* Read channel 3 */
#define ADC_CMD_SET_CHANNEL4 0x54 /* Set channel 4 */
#define ADC_CMD_READ_CHANNEL4 0x64 /* Read channel 4 */
#define ADC_CMD_SET_CHANNEL5 0x55 /* Set channel 5 */
#define ADC_CMD_READ_CHANNEL5 0x65 /* Read channel 5 */
#define ADC_CMD_SET_CHANNEL6 0x56 /* Set channel 6 */
#define ADC_CMD_READ_CHANNEL6 0x66 /* Read channel 6 */
#define ADC_CMD_SET_CHANNEL7 0x57 /* Set channel 7 */
#define ADC_CMD_READ_CHANNEL7 0x67 /* Read channel 8 */
#define ADC_CMD_SET_POWER_DOWN 0X58 /* Set ADC power down mode (1uA) */
#define ADC_CMD_SET_FAST_CONV 0X59 /* Initialize ADC Fast Convertion(<10us)*/
#define ADC_CMD_SET_LOW_CONV 0X5A /* Initialize ADC Fast Convertion(<40us)*/
#define ADC_CMD_SET_AUTOSELFT_1 0x5B /* Set Autoselft ADC {(Vref+)-(Vref-)}/2*/
#define ADC_CMD_READ_AUTOSELFT_1 0x6B /* Read Autoselft ADC 1 (0x0200) */
#define ADC_CMD_SET_AUTOSELFT_2 0x5C /* Set Autoselft ADC (Vref-) */
#define ADC_CMD_READ_AUTOSELFT_2 0x6C /* Read Autoselft ADC 2 (0x0000) */
#define ADC_CMD_SET_AUTOSELFT_3 0x5D /* Set Autoselft ADC (Vref+) */
#define ADC_CMD_READ_AUTOSELFT_3 0x6D /* Read Autoselft ADC 3 (0x03FF) */
#define ADC_SPI_CLKDIV_MIN 0x09 /* 50/(2*9) -> 2.7MHz (MAX=2.8MHz) */
#define ADC_SPI_CLKDIV_MAX 0xFF /* 50/(2*255) -> 98.04KHz */
#define ADC_MAX_BUFFER 0xFE /* 254 reads/commands */
typedef unsigned char uchar;
void jz_adc_config(JZ_REG * addr, uchar BUFFER, uchar CLK_DIV, uchar CMD);
int jz_adc_check_buffer(JZ_REG * addr);
#endif

110
Examples/ADC/src/jz_test_adc.c Normal file
View File

@ -0,0 +1,110 @@
/* ADC TEST
Copyright (C) 2010 Carlos Camargo cicamargoba@unal.edu.co
Andres Calderon andres.calderon@emqbit.com
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */
#include <stdio.h>
#include <unistd.h>
#include "jz47xx_gpio.h"
#include "jz47xx_mmap.h"
#include "jz_adc_peripheral.h"
#define TEST_PORT JZ_GPIO_PORT_B
#define TEST_PIN 26
int
main ()
{
int i,j;
JZ_PIO *pio;
JZ_REG *virt_addr;
pio = jz_gpio_map (TEST_PORT);
jz_gpio_as_func (pio, TEST_PIN, 0);
virt_addr = (JZ_REG *) (jz_mmap (0x13010000) + 0x18);
if (*virt_addr != 0x0FFF7700)
{
*virt_addr = 0x0FFF7700;
printf ("Configuring CS2 32 bits and 0 WS: %08X\n", *virt_addr);
}
else
printf ("CS2, already configured: %08X\n", *virt_addr);
virt_addr = (JZ_REG *) jz_mmap (0x14000000);
/*************************Clean FPGA RAM memory****************************/
for (i = 0; i < 512; i++) //RAMB16_s9_s9 has 2048 bytes 8-bit
{
virt_addr[i] = 0x00000000; //Clean 4 register by cicle
}
/****************Configure ADC register on FPGA RAM memory*****************/
uchar LENB = 0x01; // 1 read/cmd
jz_adc_config(virt_addr, LENB, ADC_SPI_CLKDIV_MAX, ADC_CMD_SET_SPI_CLKDIV);
usleep (100);
jz_adc_config(virt_addr, LENB, ADC_SPI_CLKDIV_MAX, ADC_CMD_SET_FAST_CONV);
usleep (100);
printf("\nADC in Fast Convertion Mode (10us) and Fs=9.8KHz (Min)\n");
LENB = ADC_MAX_BUFFER; // 254 read/cmd
/******************************* TEST 1 ***********************************/
printf("\nINIT TEST1: Autoselft {(Vref+) - (Vref-)}/2 -> Return 0x0200 \n");
jz_adc_config(virt_addr, LENB, ADC_SPI_CLKDIV_MAX, ADC_CMD_SET_AUTOSELFT_1);
usleep (100);
jz_adc_config(virt_addr, LENB, ADC_SPI_CLKDIV_MAX, ADC_CMD_READ_AUTOSELFT_1);
printf("[%08X]", virt_addr[0]);
while(jz_adc_check_buffer(virt_addr))
{
printf("[%08X]-", virt_addr[0]);
fflush (stdout);
usleep (10000);
}
for(i=1; i< LENB/2+1; i++)
printf("[%08X]", virt_addr[i]);
/******************************* TEST 2 ***********************************/
printf("\n\nINIT TEST2: Autoselft (Vref-) -> Return 0x0000 \n");
jz_adc_config(virt_addr, LENB, ADC_SPI_CLKDIV_MAX, ADC_CMD_SET_AUTOSELFT_2);
usleep (100);
jz_adc_config(virt_addr, LENB, ADC_SPI_CLKDIV_MAX, ADC_CMD_READ_AUTOSELFT_2);
while(jz_adc_check_buffer(virt_addr)){usleep (100);}
for(i=1; i< LENB/2+1; i++)
printf("[%08X]", virt_addr[i]);
/******************************* TEST 3 ***********************************/
printf("\n\nINIT TEST3: Autoselft (Vref+) -> Return 0x03FF \n");
jz_adc_config(virt_addr, LENB, ADC_SPI_CLKDIV_MAX, ADC_CMD_SET_AUTOSELFT_3);
usleep (100);
jz_adc_config(virt_addr, LENB, ADC_SPI_CLKDIV_MAX, ADC_CMD_READ_AUTOSELFT_3);
while(jz_adc_check_buffer(virt_addr)){usleep (100);}
for(i=1; i< LENB/2+1; i++)
printf("[%08X]", virt_addr[i]);
printf("\n\nTESTS complete\n");
LENB = 0x01; // 1 read/cmd
jz_adc_config(virt_addr, LENB, ADC_SPI_CLKDIV_MAX, ADC_CMD_SET_POWER_DOWN);
printf("\nADC in Power Down Mode \n");
return 0;
}