Adding post route simulation to FPGA examples

Examples/blink/logic/Makefile

@@ -16,7 +16,7 @@ all:            bits
 remake:         clean-build all
 
 clean:
-	rm -f *~ */*~ a.out *.log *.key *.edf *.ps trace.dat
+	rm -f *~ */*~ a.out *.log *.key *.edf *.ps trace.dat 
 	rm -f *.bit
 
 cleanall: clean
@@ -63,8 +63,15 @@ build/project_r.twr: build/project_r.ncd
 $(DESIGN).bit:  build/project_r.ncd build/project_r.twr
 	cd build && bitgen project_r.ncd -l -w $(BGFLAGS)
 	@mv -f build/project_r.bit $@
+
+build/project_r.v: build/project_r.ncd
+	cd build &&  netgen -sim -ofmt vhdl project_r.ncd -pcf project.pcf && ngd2ver project.ngd  -w project.v
+
 sim: 
-	cd simulation; $(SIM_CMD) -do $(DESIGN)_TB.do 
+	cd simulation; $(SIM_CMD) -do $(DESIGN)_TB.do
+
+timesim: build/project_r.v
+	cd simulation; $(SIM_CMD) -do $(DESIGN)_TIMING_TB.do
 
 upload: $(DESIGN).bit
 	scp $(DESIGN).bit root@$(SAKC_IP): 

Examples/blink/logic/simulation/blink_TB.do

@@ -1,11 +1,13 @@
 vlib work
-vlog  +acc  "../blink.v"
-vlog  +acc  "../blink_TB.v"
-vlog  +acc  "glbl.v"
-vsim -t 1ps   -L xilinxcorelib_ver -L unisims_ver  blink_TB_v glbl
+vlog   -incr +libext+.v                    \
+			"../blink.v"       \
+			"../blink_TB.v"    \
+			"glbl.v"
+
+vsim -t 1ps -L simprims_ver -L unisims_ver -L xilinxcorelib_ver blink_TB_v glbl
 view wave
-do wave.do
-#add wave *
+#do wave.do
+add wave *
 add wave /glbl/GSR
 view structure
 view signals

Examples/blink/logic/simulation/blink_TIMING_TB.do

@@ -0,0 +1,10 @@
+vlib work
+vlog   -incr "../build/project.v" "../blink_TB.v" "glbl.v"
+vsim -t 1ps -L simprims_ver -L unisims_ver -L xilinxcorelib_ver   blink_TB_v glbl
+view wave
+#do wave.do
+add wave *
+add wave /glbl/GSR
+view structure
+view signals
+run 15ms