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Adding post route simulation to FPGA examples

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This commit is contained in:
Carlos Camargo
2010-05-10 14:56:51 -05:00
parent 5938d6531c
commit 717c35e238
23 changed files with 404 additions and 15 deletions
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11
Examples/blink/logic/Makefile
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@@ -16,7 +16,7 @@ all: bits
remake: clean-build all
clean:
rm -f *~ */*~ a.out *.log *.key *.edf *.ps trace.dat
rm -f *~ */*~ a.out *.log *.key *.edf *.ps trace.dat
rm -f *.bit
cleanall: clean
@@ -63,8 +63,15 @@ build/project_r.twr: build/project_r.ncd
$(DESIGN).bit: build/project_r.ncd build/project_r.twr
cd build && bitgen project_r.ncd -l -w $(BGFLAGS)
@mv -f build/project_r.bit $@
build/project_r.v: build/project_r.ncd
cd build && netgen -sim -ofmt vhdl project_r.ncd -pcf project.pcf && ngd2ver project.ngd -w project.v
sim:
cd simulation; $(SIM_CMD) -do $(DESIGN)_TB.do
cd simulation; $(SIM_CMD) -do $(DESIGN)_TB.do
timesim: build/project_r.v
cd simulation; $(SIM_CMD) -do $(DESIGN)_TIMING_TB.do
upload: $(DESIGN).bit
scp $(DESIGN).bit root@$(SAKC_IP):