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Adding post route simulation to FPGA examples

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This commit is contained in:
Carlos Camargo
2010-05-10 14:56:51 -05:00
parent 5938d6531c
commit 717c35e238
23 changed files with 404 additions and 15 deletions
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10
Examples/sram/logic/Makefile
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@@ -6,7 +6,6 @@ BGFLAGS = -g TdoPin:PULLNONE -g DonePin:PULLUP \
SIM_CMD = /opt/cad/modeltech/bin/vsim
SIM_COMP_SCRIPT = simulation/$(DESIGN)_TB.do
#SIM_INIT_SCRIPT = simulation/$(DESIGN)_init.do
SIMGEN_OPTIONS = -p $(FPGA_ARCH) -lang $(LANGUAGE)
SAKC_IP = 192.168.254.101
@@ -67,8 +66,15 @@ build/project_r.twr: build/project_r.ncd
$(DESIGN).bit: build/project_r.ncd build/project_r.twr
cd build && bitgen project_r.ncd -l -w $(BGFLAGS)
@mv -f build/project_r.bit $@
build/project_r.v: build/project_r.ncd
cd build && netgen -sim -ofmt vhdl project_r.ncd -pcf project.pcf && ngd2ver project.ngd -w project.v
sim:
cd simulation; $(SIM_CMD) -do $(DESIGN)_TB.do
cd simulation; $(SIM_CMD) -do $(DESIGN)_TB.do
timesim: build/project_r.v
cd simulation; $(SIM_CMD) -do $(DESIGN)_TIMING_TB.do
upload: $(DESIGN).bit
scp $(DESIGN).bit root@$(SAKC_IP):