Adding post route simulation to FPGA examples

Examples/sram/logic/simulation/work/_info

@@ -0,0 +1,32 @@
+m255
+13
+cModel Technology
+d/home/cain/Embedded/ingenic/sakc/nn-usb-fpga/Examples/sram/logic/simulation
+vglbl
+IT?5S;>bN`@zG_25]R_4A33
+VnN]4Gon>inod6>M^M2[SV1
+w1273510321
+Fglbl.v
+L0 5
+OE;L;6.0d;29
+r1
+31
+vsram_bus
+IYS7oKaz71LdIhQ>[[g2fo3
+V7bnNHP1kz?3UaZfjPj4WE1
+w1273511584
+F../build/project.v
+L0 37
+OE;L;6.0d;29
+r1
+31
+vsram_bus_TB_v
+IA=m;kT@<eh:`ekMlOPXX@0
+VQ[@Nfjd=de;Dc[[gj0bf41
+w1273511227
+F../sram_bus_TB.v
+L0 3
+OE;L;6.0d;29
+r1
+31
+nsram_bus_@t@b_v

Examples/sram/logic/simulation/work/glbl/_primary.vhd

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+library verilog;
+use verilog.vl_types.all;
+entity glbl is
+    generic(
+        ROC_WIDTH       : integer := 100000;
+        TOC_WIDTH       : integer := 0
+    );
+end glbl;

Examples/sram/logic/simulation/work/sram_bus/_primary.vhd

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+library verilog;
+use verilog.vl_types.all;
+entity sram_bus is
+    port(
+        clk             : in     vl_logic;
+        reset           : in     vl_logic;
+        ncs             : in     vl_logic;
+        noe             : in     vl_logic;
+        nwe             : in     vl_logic;
+        led             : out    vl_logic;
+        sram_data       : inout  vl_logic_vector(7 downto 0);
+        addr            : in     vl_logic_vector(12 downto 0)
+    );
+end sram_bus;

Examples/sram/logic/simulation/work/sram_bus_@t@b_v/_primary.vhd

@@ -0,0 +1,13 @@
+library verilog;
+use verilog.vl_types.all;
+entity sram_bus_TB_v is
+    generic(
+        PERIOD          : integer := 20;
+        DUTY_CYCLE      : real    := 0.500000;
+        OFFSET          : integer := 0;
+        TSET            : integer := 3;
+        THLD            : integer := 3;
+        NWS             : integer := 3;
+        CAM_OFF         : integer := 4000
+    );
+end sram_bus_TB_v;