mirror of
git://projects.qi-hardware.com/nn-usb-fpga.git
synced 2025-01-23 11:01:06 +02:00
Fixing LOGIC example.
This commit is contained in:
Juan64Bits
parent
062270bbd4
commit
7545f04d37
@ -3,8 +3,8 @@ NET reset LOC = "P71"; #WARNING change to another pin
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NET led LOC = "P44";
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#ADDRESS BUS
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#NET "addr<12>" LOC = "P90";
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#NET "addr<11>" LOC = "P91";
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NET "addr<12>" LOC = "P90";
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NET "addr<11>" LOC = "P91";
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NET "addr<10>" LOC = "P85";
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NET "addr<9>" LOC = "P92";
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NET "addr<8>" LOC = "P94";
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@ -38,4 +38,4 @@ NET "ADC_SCLK" LOC = "P18" ;
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NET "ADC_SDIN" LOC = "P22";
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NET "ADC_SDOUT" LOC = "P23";
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NET "ADC_CS" LOC = "P24";
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NET "ADC_CSTART" LOC = "P26";
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NET "ADC_CSTART" LOC = "P26";
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@ -15,7 +15,7 @@ module ADC(clk, sram_data, addr, nwe, ncs, noe, reset, led, ADC_EOC,
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// synchronize signals
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reg sncs, snwe;
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reg [10:0] buffer_addr;
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reg [12:0] buffer_addr;
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reg [B:0] buffer_data;
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// bram interfaz signals
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@ -25,7 +25,7 @@ module ADC(clk, sram_data, addr, nwe, ncs, noe, reset, led, ADC_EOC,
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wire [B:0] rdBus;
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// interfaz fpga signals
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wire [10:0] addr;
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wire [12:0] addr;
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reg [25:0] counter;
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@ -76,14 +76,14 @@ module ADC(clk, sram_data, addr, nwe, ncs, noe, reset, led, ADC_EOC,
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wire [3:0] csN;
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wire [7:0] rdBus0, rdBus1, rdBus2, rdBus3;
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assign csN = buffer_addr[10]? (buffer_addr[9]? 4'b1000:
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assign csN = buffer_addr[12]? (buffer_addr[11]? 4'b1000:
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4'b0100)
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: (buffer_addr[9]? 4'b0010:
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: (buffer_addr[11]? 4'b0010:
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4'b0001);
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assign rdBus = buffer_addr[10]? (buffer_addr[9]? rdBus3:
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assign rdBus = buffer_addr[12]? (buffer_addr[11]? rdBus3:
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rdBus2)
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: (buffer_addr[9]? rdBus1:
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: (buffer_addr[11]? rdBus1:
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rdBus0);
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// Peripheral instantiation
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@ -97,7 +97,7 @@ module ADC(clk, sram_data, addr, nwe, ncs, noe, reset, led, ADC_EOC,
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.ADC_SCLK(ADC_SCLK),
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.ADC_SDIN(ADC_SDIN),
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.ADC_SDOUT(ADC_SDOUT),
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.addr(buffer_addr[8:0]),
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.addr(buffer_addr[10:0]),
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.rdBus(rdBus0),
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.wrBus(wrBus),
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.we(we));
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@ -4,39 +4,53 @@ module ADC_peripheral( clk, reset, cs, ADC_EOC, ADC_CS, ADC_CSTART,
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addr, rdBus, wrBus, we);
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input clk, reset, ADC_EOC, cs, we;
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input [8:0] addr;
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input [10:0] addr;
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input [7:0] wrBus;
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output ADC_CS, ADC_CSTART, ADC_SCLK;
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output [7:0] rdBus;
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inout ADC_SDIN, ADC_SDOUT;
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//RAMB registers
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reg [7:0] rdBus;
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wire [7:0] rdBus1;
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wire [7:0] rdBus2;
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reg [7:0] wrBus2;
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reg [8:0] addr2;
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wire we1;
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reg we2=0, nSample=0;
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reg [7:0] auto_count=0;
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reg [10:0] addr2;
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reg we1=0;
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reg we2=0;
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wire we;
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//Control registers
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reg nSample=0;
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reg [10:0] auto_count=0;
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reg [4:0] w_st2=0;
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//SPI registers
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reg [3:0] SPI_in_data=0;
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reg [9:0] SPI_out_data;
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reg SPI_rd = 0;
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reg SPI_wr = 0;
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reg [7:0] buffer_rd1;
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reg [3:0] ADC_cmd;
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assign we1 = we & cs;
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reg SPI_wr = 0;
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// Confiuration registers
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reg CMD_DONE;
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reg CMD_TYP;
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reg [3:0] CMD_ADC;
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reg [7:0] CLKDIV = 0;
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reg [10:0] SIZEB; //[10:8] -> size_hi | [7:0] -> size_low
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//TEMPS
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reg [10:0] SIZEB2;
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reg CMD_DONE2;
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assign ADC_CSTART = 1'b1;
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// Dual-port RAM instatiation
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RAMB16_S9_S9 ba0(
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.DOA(rdBus), // Port A 8-bit Data Output
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.DOA(rdBus1), // Port A 8-bit Data Output
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.DOB(rdBus2), // Port B 8-bit Data Output
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.DOPA(), // Port A 1-bit Parity Output
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.DOPB(), // Port B 1-bit Parity Output
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.ADDRA(addr[8:0]), // Port A 11-bit Address Input
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.ADDRB(addr2[8:0]), // Port B 11-bit Address Input
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.ADDRA(addr[10:0]), // Port A 11-bit Address Input
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.ADDRB(addr2[10:0]), // Port B 11-bit Address Input
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.CLKA(~clk), // Port A Clock
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.CLKB(~clk), // Port B Clock
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.DIA(wrBus), // Port A 8-bit Data Input
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@ -58,12 +72,11 @@ module ADC_peripheral( clk, reset, cs, ADC_EOC, ADC_CS, ADC_CSTART,
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reg [3:0] in_buffer=0;
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reg [9:0] out_buffer;
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reg [7:0] clkcount = 0;
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reg [7:0] clkdiv = 255;
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reg [4:0] count = 0;
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assign ADC_CS = ~busy;
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always@(SPI_rd or out_buffer or busy or clkdiv)
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always@(SPI_rd or out_buffer or busy or CLKDIV)
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begin
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SPI_out_data = 10'bx;
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if(SPI_rd)
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@ -80,7 +93,7 @@ module ADC_peripheral( clk, reset, cs, ADC_EOC, ADC_CS, ADC_CSTART,
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else
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begin
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clkcount = clkcount + 1;
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if(clkcount >= clkdiv)
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if(clkcount >= CLKDIV)
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begin
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clkcount = 0;
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// Send the ADC CMD on first 4 rising edge of SCLK
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@ -113,46 +126,63 @@ module ADC_peripheral( clk, reset, cs, ADC_EOC, ADC_CS, ADC_CSTART,
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assign ADC_SCLK = ADC_SCLK_buffer;
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assign ADC_SDIN = ADC_SDIN_buffer;
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// State Machine for control ADC comunication
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// Write control
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always @(negedge clk)
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if(reset)
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{CMD_TYP,CMD_ADC,SIZEB,we1} <= 0;
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else if(we & cs) begin
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case (addr)
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0: begin CMD_TYP <= wrBus[4];
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CMD_ADC[3:0] <= wrBus[3:0]; end
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1: begin CLKDIV <= wrBus; end
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2: begin SIZEB[7:0] <= wrBus; end
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3: begin SIZEB[10:8] <= wrBus[2:0]; end
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default: begin we1 <= 1; end
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endcase
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end
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else if(nSample)
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begin SIZEB <= SIZEB - 1; end
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else
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begin we1 <= 0; end
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// Read control
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always @(posedge clk)
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if(reset)
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{rdBus} <= 0;
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else begin
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case (addr)
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0: begin rdBus <= {CMD_DONE,CMD_TYP,CMD_ADC};end
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1: begin rdBus <= CLKDIV; end
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2: begin rdBus <= SIZEB[7:0]; end
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3: begin rdBus <= SIZEB[10:8]; end
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default: begin rdBus <= rdBus1; end
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endcase
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end
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// Comunication control
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always @(posedge clk)
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if(reset)
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{we2, SPI_wr, SPI_rd, w_st2, auto_count, SPI_in_data} <= 0;
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{we2, SPI_wr, SPI_rd, w_st2, auto_count, SPI_in_data, nSample} <= 0;
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else begin
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case (w_st2)
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0: begin addr2 <= 0; w_st2 <= 1; end
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1: begin
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ADC_cmd <= rdBus2[3:0];
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if (rdBus2[7:4] == 5)
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// Send command without read samples
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begin addr2<= 2; w_st2 <= 2; nSample <= 1; end
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else if (rdBus2[7:4] == 6)
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// Read: Stop when buffer full
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begin addr2<= 2; w_st2 <= 2; nSample <= 0; end
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else if (rdBus2[7:4] == 9)
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// Set clkdiv on SPI controller
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begin addr2<= 1; w_st2 <= 10; end
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else
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begin w_st2 <= 0; end
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end
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0: begin w_st2 <= 2; SIZEB2<=SIZEB; end
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2: begin
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if (rdBus2[7:0] == 0)
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begin auto_count<=0; w_st2 <= 0; end
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if (SIZEB == 0)
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begin w_st2 <= 0; CMD_DONE<= 1; auto_count <= 0; end
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else begin
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CMD_DONE<= 0;
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//Send data to ADC
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buffer_rd1<=rdBus2;
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auto_count<=auto_count+1;
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SPI_in_data <= ADC_cmd[3:0];
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SPI_wr <= 1; w_st2 <= 3;
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auto_count <= auto_count+1;
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SPI_in_data <= CMD_ADC[3:0];
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SPI_wr <= 1; w_st2 <= 3;
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end
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end
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3: begin
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SPI_wr <= 0;
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SPI_wr <= 0;
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//Wait for complete convertion
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if(!ADC_EOC || ADC_CS) begin
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buffer_rd1<=buffer_rd1-1;
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SPI_rd <=1;
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if(nSample)
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w_st2<= 8;
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if(CMD_TYP)
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w_st2<= 2;
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else
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w_st2<= 4;
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end
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@ -160,29 +190,18 @@ module ADC_peripheral( clk, reset, cs, ADC_EOC, ADC_CS, ADC_CSTART,
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4: begin
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//Write data on BRAM (LOW)
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wrBus2 <= SPI_out_data[7:0];
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addr2 <= 2+2*auto_count;
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addr2 <= 4+2*(SIZEB2-SIZEB);
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we2 <= 1; w_st2 <= 5;
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end
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5: begin we2 <= 0; w_st2 <= 6; end
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5: begin we2 <= 0; w_st2 <= 6; end
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6: begin
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//Write data on BRAM (HI)
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wrBus2 <= SPI_out_data[9:8];
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addr2 <= 3+2*auto_count;
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we2 <= 1; w_st2 <= 7;
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addr2 <= 5+2*(SIZEB2-SIZEB);
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we2 <= 1; w_st2 <= 7; nSample <= 1;
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end
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7: begin we2 <= 0; w_st2 <= 8; end
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8: begin
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SPI_rd <=0;
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//Update Buffer Size value
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wrBus2 <= buffer_rd1;
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addr2 <= 2;
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we2 <= 1; w_st2 <= 9;
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end
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9: begin we2 <= 0; w_st2 <= 0; end
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//Sent clock divider for speed on SPI comunication
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10: begin clkdiv = rdBus2; w_st2 <= 0; end
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7: begin nSample <= 0; we2 <= 0; SPI_rd <=0; w_st2 <= 2; end
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endcase
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end
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endmodule
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endmodule
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