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Code

lm32 loader

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This commit is contained in:
carlos 2010-10-13 08:49:36 -05:00
parent ece832aa3a
commit 7b666c041a
9 changed files with 53 additions and 293 deletions
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3
lm32/logic/sakc/firmware/boot0-serial/Makefile
View File

@ -4,14 +4,13 @@ LM32_OBJCOPY=lm32-elf-objcopy
LM32_OBJDUMP=lm32-elf-objdump
SREC2VRAM ?= ../../tools/srec2vram/srec2vram
VRAMFILE=image.ram
CFLAGS=-MMD -O2 -Wall -g -s -fomit-frame-pointer -mbarrel-shift-enabled -mmultiply-enabled -mdivide-enabled -msign-extend-enabled
LDFLAGS=-nostdlib -nodefaultlibs -Tlinker.ld
SEGMENTS = -j .text -j .rodata -j .data
all: $(VRAMFILE)
all: image.srec $(VRAMFILE)
crt0ram.o: crt0ram.S
$(LM32_CC) $(CFLAGS) -c crt0ram.S

14
lm32/logic/sakc/firmware/loader_cain/Makefile
View File

@ -21,25 +21,27 @@ main.o: main.c
soc-hw.o: soc-hw.c
$(LM32_CC) $(CFLAGS) -c soc-hw.c
xmodem.o: xmodem.c
$(LM32_CC) $(CFLAGS) -c xmodem.c
image: crt0ram.o main.o soc-hw.o xmodem.o linker.ld Makefile
$(LM32_LD) $(LDFLAGS) -Map image.map -N -o image crt0ram.o main.o soc-hw.o xmodem.o
image: crt0ram.o main.o soc-hw.o xmodem.o
$(LM32_LD) $(LDFLAGS) -Map image.map -N -o image crt0ram.o main.o soc-hw.o xmodem.o
image.lst: image
$(LM32_OBJDUMP) -h -S $< > $@
image.bin: image
$(LM32_OBJCOPY) $(SEGMENTS) -O binary image image.bin
$(LM32_OBJCOPY) $(SEGMENTS) -O srec image image.bin
$(LM32_OBJCOPY) $(SEGMENTS) -O binary image image_bin.bin
image.srec: image image.lst
$(LM32_OBJCOPY) $(SEGMENTS) -O srec image image.srec
$(VHDLFILE): image.srec
$(SREC2VHDL) image.srec > $(VHDLFILE)
$(VRAMFILE): image.srec
$(SREC2VRAM) image.srec 0x0000000 0x1000 > $(VRAMFILE)
$(SREC2VRAM) image.srec 0x00000000 0x1000 > $(VRAMFILE)
clean:
rm -f image image.lst image.bin image.srec image.map image.ram *.o *.d

180
lm32/logic/sakc/firmware/loader_cain/crt0ram.S
View File

@ -24,12 +24,9 @@
*/
/* Exception handlers - Must be 32 bytes long. */
.section .text, "ax", @progbits
.global _start
.global irq_enable, irq_disable, irq_set_mask, irq_get_mask
.global jump, halt
.global get_sp, get_gp
.section .text, "ax", @progbits
.global _start
.global irq_enable, irq_disable, irq_mask, jump, halt
_start:
_reset_handler:
xor r0, r0, r0
@ -41,76 +38,6 @@ _reset_handler:
nop
nop
_breakpoint_handler:
nop
nop
nop
nop
nop
nop
nop
nop
_ibuserror_handler:
nop
nop
nop
nop
nop
nop
nop
nop
_watchpoint_handler:
nop
nop
nop
nop
nop
nop
nop
nop
_dbuserror_handler:
nop
nop
nop
nop
nop
nop
nop
nop
_divzero_handler:
nop
nop
nop
nop
nop
nop
nop
nop
_interrupt_handler:
sw (sp+0), ra
calli _save_all
rcsr r1, IP
calli irq_handler
mvhi r1, 0xffff
ori r1, r1, 0xffff
wcsr IP, r1
bi _restore_all_and_eret
_scall_handler:
nop
nop
nop
nop
nop
nop
nop
nop
_crt0:
/* Setup stack and global pointer */
mvhi sp, hi(_fstack)
@ -140,110 +67,19 @@ irq_enable:
wcsr IE, r1
ret
irq_mask:
mvi r1, 0x0000000f
wcsr IM, r1
ret
irq_disable:
mvi r1, 0
wcsr IE, r1
ret
irq_set_mask:
wcsr IM, r1
ret
irq_get_mask:
rcsr r1, IM
ret
jump:
b r1
halt:
bi halt
/* Save all registers onto the stack */
_save_all:
addi sp, sp, -128
sw (sp+4), r1
sw (sp+8), r2
sw (sp+12), r3
sw (sp+16), r4
sw (sp+20), r5
sw (sp+24), r6
sw (sp+28), r7
sw (sp+32), r8
sw (sp+36), r9
sw (sp+40), r10
#ifdef MICO32_FULL_CONTEXT_SAVE_RESTORE
sw (sp+44), r11
sw (sp+48), r12
sw (sp+52), r13
sw (sp+56), r14
sw (sp+60), r15
sw (sp+64), r16
sw (sp+68), r17
sw (sp+72), r18
sw (sp+76), r19
sw (sp+80), r20
sw (sp+84), r21
sw (sp+88), r22
sw (sp+92), r23
sw (sp+96), r24
sw (sp+100), r25
sw (sp+104), r26
sw (sp+108), r27
#endif
sw (sp+120), ea
sw (sp+124), ba
/* ra and sp need special handling, as they have been modified */
lw r1, (sp+128)
sw (sp+116), r1
mv r1, sp
addi r1, r1, 128
sw (sp+112), r1
ret
/* Restore all registers and return from exception */
_restore_all_and_eret:
lw r1, (sp+4)
lw r2, (sp+8)
lw r3, (sp+12)
lw r4, (sp+16)
lw r5, (sp+20)
lw r6, (sp+24)
lw r7, (sp+28)
lw r8, (sp+32)
lw r9, (sp+36)
lw r10, (sp+40)
#ifdef MICO32_FULL_CONTEXT_SAVE_RESTORE
lw r11, (sp+44)
lw r12, (sp+48)
lw r13, (sp+52)
lw r14, (sp+56)
lw r15, (sp+60)
lw r16, (sp+64)
lw r17, (sp+68)
lw r18, (sp+72)
lw r19, (sp+76)
lw r20, (sp+80)
lw r21, (sp+84)
lw r22, (sp+88)
lw r23, (sp+92)
lw r24, (sp+96)
lw r25, (sp+100)
lw r26, (sp+104)
lw r27, (sp+108)
#endif
lw ra, (sp+116)
lw ea, (sp+120)
lw ba, (sp+124)
/* Stack pointer must be restored last, in case it has been updated */
lw sp, (sp+112)
eret
get_sp:
mv r1, sp
ret
get_gp:
mv r1, gp
ret

18
lm32/logic/sakc/firmware/loader_cain/linker.ld
View File

@ -4,12 +4,12 @@ ENTRY(_start)
__DYNAMIC = 0;
_RAM_START = 0x0000000;
_RAM_SIZE = 0x1000;
_RAM_END = _RAM_START + _RAM_SIZE;
_BRAM_START = 0x00000000;
_BRAM_SIZE = 0x1000;
_BRAM_END = _BRAM_START + _BRAM_SIZE;
MEMORY {
ram : ORIGIN = 0x0000000, LENGTH = 0x1000 /* 4k */
bram : ORIGIN = 0x00000000, LENGTH = 0x1000 /* 4k */
}
SECTIONS
@ -19,7 +19,7 @@ SECTIONS
_ftext = .;
*(.text .stub .text.* .gnu.linkonce.t.*)
_etext = .;
} > ram
} > bram
.rodata :
{
@ -28,7 +28,7 @@ SECTIONS
*(.rodata .rodata.* .gnu.linkonce.r.*)
*(.rodata1)
_erodata = .;
} > ram
} > bram
.data :
{
@ -39,7 +39,7 @@ SECTIONS
_gp = ALIGN(16);
*(.sdata .sdata.* .gnu.linkonce.s.*)
_edata = .;
} > ram
} > bram
.bss :
{
@ -53,7 +53,7 @@ SECTIONS
*(COMMON)
_ebss = .;
_end = .;
} > ram
} > bram
}
PROVIDE(_fstack = ORIGIN(ram) + LENGTH(ram) - 4);
PROVIDE(_fstack = ORIGIN(bram) + LENGTH(bram) - 4);

42
lm32/logic/sakc/firmware/loader_cain/main.c
View File

@ -1,55 +1,41 @@
/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
#include "soc-hw.h"
#define RAM_BASE 0x1000
unsigned int i, j,k; // Loop counter.
int main() {
int key, len, autoboot = 1, dispmenu = 1;
int key, len, autoboot = 1, dispmenu = 1;
uart_init();
uart_putstr("Cain's bootloader!!! \n");
uart_putstr("Cain's bootloader!!! \r\n");
while(1){ /* loop forever until u-boot gets booted or the board is reset */
if(dispmenu){
uart_putstr("\n1: Upload program to RAM\n");
// uart_putstr("2: Upload u-boot to Dataflash\n");
// uart_putstr("3: Upload Kernel to Dataflash\n");
// uart_putstr("4: Start u-boot\n");
// uart_putstr("5: Upload Filesystem image\n");
// uart_putstr("6: Memory test\n");
uart_putstr("\n1: Upload program to RAM\r\n");
// uart_putstr("2: Upload u-boot to Dataflash\r\n");
// uart_putstr("3: Upload Kernel to Dataflash\r\n");
// uart_putstr("4: Start u-boot\r\n");
// uart_putstr("5: Upload Filesystem image\r\n");
// uart_putstr("6: Memory test\r\n");
dispmenu = 0;
}
key = uart_getchar();
autoboot = 0;
if(key == '1'){
len = rxmodem((char *)0x1000);
len = rxmodem((unsigned char *)0x1000);
uart_putstr("Received ");
hexprint(len);
uart_putstr(" bytes\n");
jump(RAM_BASE);
// dispmenu = 1;
}
else if(key == '2'){
uart_putstr(" bytes\r\n");
// jump(RAM_BASE);
dispmenu = 1;
}
else{
uart_putstr("Invalid input\n");
uart_putstr("Invalid input\r\n");
dispmenu = 1;
}
}
while(1){ asm("nop;"); }
while(1){ asm("nop;"); }
return (0);
return (0);
}

84
lm32/logic/sakc/firmware/loader_cain/soc-hw.c
View File

@ -1,58 +1,22 @@
#include "soc-hw.h"
uart_t *uart0 = (uart_t *) 0xf0000000;
timer_t *timer0 = (timer_t *) 0xf0010000;
uart_t *uart0 = (uart_t *) 0xF0000000;
timer_t *timer0 = (timer_t *) 0xF0010000;
gpio_t *gpio0 = (gpio_t *) 0xF0020000;
isr_ptr_t isr_table[32];
void tic_isr();
/***************************************************************************
* IRQ handling
*/
void isr_null()
{
}
void irq_handler(uint32_t pending)
{
int i;
for(i=0; i<32; i++) {
if (pending & 0x01) (*isr_table[i])();
pending >>= 1;
}
}
void isr_init()
{
int i;
for(i=0; i<32; i++)
isr_table[i] = &isr_null;
}
void isr_register(int irq, isr_ptr_t isr)
{
isr_table[irq] = isr;
}
void isr_unregister(int irq)
{
isr_table[irq] = &isr_null;
}
uint32_t msec = 0;
/***************************************************************************
* TIMER Functions
* General utility functions
*/
void msleep(uint32_t msec)
void sleep(int msec)
{
uint32_t tcr;
// Use timer0.1
timer0->compare1 = (FCPU/1000)*msec;
timer0->counter1 = 0;
timer0->tcr1 = TIMER_EN;
timer0->tcr1 = TIMER_EN | TIMER_IRQEN;
do {
//halt();
@ -60,43 +24,14 @@ void msleep(uint32_t msec)
} while ( ! (tcr & TIMER_TRIG) );
}
void nsleep(uint32_t nsec)
{
uint32_t tcr;
// Use timer0.1
timer0->compare1 = (FCPU/1000000)*nsec;
timer0->counter1 = 0;
timer0->tcr1 = TIMER_EN;
do {
//halt();
tcr = timer0->tcr1;
} while ( ! (tcr & TIMER_TRIG) );
}
uint32_t tic_msec;
void tic_isr()
{
tic_msec++;
timer0->tcr0 = TIMER_EN | TIMER_AR | TIMER_IRQEN;
}
void tic_init()
{
tic_msec = 0;
// Setup timer0.0
timer0->compare0 = (FCPU/10000);
timer0->compare0 = (FCPU/1000);
timer0->counter0 = 0;
timer0->tcr0 = TIMER_EN | TIMER_AR | TIMER_IRQEN;
isr_register(1, &tic_isr);
}
/***************************************************************************
* UART Functions
*/
@ -143,11 +78,12 @@ void hexprint(unsigned int hexval)
for(pos = 7; pos > -1; pos--)
{
if(digit[pos] < 0xA)
uart_putstr(digit[pos] + '0');
uart_putstr((char *)digit[pos] + '0');
else
uart_putstr(digit[pos] + 'A' - 10);
uart_putstr((char *)digit[pos] + 'A' - 10);
}
uart_putchar(' ');
}

3
lm32/logic/sakc/firmware/loader_cain/soc-hw.h
View File

@ -95,7 +95,6 @@ void uart_init();
void uart_putchar(char c);
void uart_putstr(char *str);
char uart_getchar();
void hexprint(unsigned int hexval);
/***************************************************************************
@ -106,7 +105,7 @@ extern uart_t *uart0;
extern gpio_t *gpio0;
extern uint32_t *sram0;
int rxmodem(unsigned char *dest);
void hexprint(unsigned int hexval);
#endif // SPIKEHW_H

1
lm32/logic/sakc/firmware/loader_cain/xmodem.c
View File

@ -18,6 +18,7 @@
*/
#include "soc-hw.h"
#define SOH 0x01
#define EOT 0x04
#define ACK 0x06

1
lm32/logic/sakc/system.v
View File

@ -7,6 +7,7 @@
module system
#(
parameter bootram_file = "../firmware/loader_cain/image.ram",
// parameter bootram_file = "../firmware/boot0-serial/image.ram",
parameter clk_freq = 50000000,
parameter uart_baud_rate = 57600
) (