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This commit is contained in:
César Pedraza
2010-10-12 10:11:07 -05:00
parent 9b75552c83
commit c48feff62c
16 changed files with 1618 additions and 347 deletions
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208
Examples/ehw4/logic/ehw.v
View File

@@ -12,14 +12,13 @@ module ehw(clk, sram_data, addr, nwe, ncs, noe, reset, led,
// synchronize signals
reg sncs, snwe;
reg [12:0] buffer_addr;
reg [B:0] buffer_data;
wire led;
reg [B:0] buffer_data;
// bram-cpu interfaz
reg we;
reg w_st=0;
reg [B:0] wdBus;
reg [B:0] rdBus;
wire [B:0] rdBus;
wire [12:0] addr;
reg [7:0] bae;
@@ -45,11 +44,7 @@ module ehw(clk, sram_data, addr, nwe, ncs, noe, reset, led,
wire [3:0] max_lev;
wire [7:0] control;
reg [7:0] reg_bank [31:0];
wire enReg;
wire [4:0] address;
// Test : LED blinking
// Test : LED blinking
reg [25:0] counter;
always @(posedge clk) begin
if (~reset)
@@ -59,11 +54,11 @@ module ehw(clk, sram_data, addr, nwe, ncs, noe, reset, led,
end
assign led = counter[24];
// Data Bus direction control
// Data Bus direction control
wire T = ~noe | ncs;
assign sram_data = T?8'bZ:rdBus;
// synchronize assignment
// synchronize assignment
always @(negedge clk)
begin
sncs <= ncs;
@@ -72,7 +67,7 @@ module ehw(clk, sram_data, addr, nwe, ncs, noe, reset, led,
buffer_addr <= addr;
end
// write access cpu to bram
// write access cpu to bram
always @(posedge clk)
if(~reset) {w_st, we, wdBus} <= 0;
else begin
@@ -115,164 +110,63 @@ module ehw(clk, sram_data, addr, nwe, ncs, noe, reset, led,
else
bae <= 8'h00;
end
wire en1, en2; // enable memory signals
assign en0 = bae[0] | bae[1] | bae[2] | bae[3];
assign en1 = bae[4] | bae[5] | bae[6] | bae[7];
reg[31:0] DIA_Aux;
always @ (posedge clk) begin
if (bae[0]) DIA_Aux[7:0] = wdBus[7:0];
if (bae[1]) DIA_Aux[15:8] = wdBus[7:0];
if (bae[2]) DIA_Aux[23:16] = wdBus[7:0];
if (bae[3]) DIA_Aux[31:24] = wdBus[7:0];
if (bae[4]) DIA_Aux[7:0] = wdBus[7:0];
if (bae[5]) DIA_Aux[15:8] = wdBus[7:0];
if (bae[6]) DIA_Aux[23:16] = wdBus[7:0];
if (bae[7]) DIA_Aux[31:24] = wdBus[7:0];
end
reg [2:0] state, nextstate; //FSM for write in 32bit mode to memory
wire we0, we1;
wire nreset;
assign nreset = ~reset;
parameter S0 = 3'b000;
parameter S1 = 3'b001;
parameter S2 = 3'b010;
always @ (posedge clk, posedge nreset)
if (nreset) state <= S0;
else state <= nextstate;
// next state logic
always@(*)
case (state)
S0:if (bae[3]&we) nextstate = S1;
else
if (bae[7]&we) nextstate = S2;
else nextstate = S0;
S1: nextstate = S0;
S2: nextstate = S0;
default: nextstate = S0;
endcase
// output logic
assign we0 = (state == S1);
assign we1 = (state == S2);
// Memories
// Read control
reg [7:0] MemDOA;
wire [63:0] DOA_Aux;
always @(posedge clk)
if(~reset)begin
rdBus = 8'h00;
end
else begin
if(enReg)
rdBus = reg_bank[address];
else
rdBus = MemDOA[7:0];
end
// memory output mux
always @(buffer_addr[2:0])
case (buffer_addr[2:0])
0 : MemDOA = DOA_Aux[7:0];
1 : MemDOA = DOA_Aux[15:8];
2 : MemDOA = DOA_Aux[23:16];
3 : MemDOA = DOA_Aux[31:24];
4 : MemDOA = DOA_Aux[39:32];
5 : MemDOA = DOA_Aux[47:40];
6 : MemDOA = DOA_Aux[55:48];
7 : MemDOA = DOA_Aux[63:56];
default: MemDOA = 8'h00;
endcase
// Store Inputs
always @(posedge clk)
begin
if(enReg) begin
reg_bank[20] = error[7:0];
reg_bank[21] = error[15:8];
reg_bank[22] = status[7:0];
reg_bank[24] = mt_rnd[7:0];
reg_bank[25] = mt_rnd[15:8];
reg_bank[26] = mt_rnd[23:16];
reg_bank[27] = mt_rnd[31:24];
end
end
RAMB16_S4_S4 ba0( .CLKA(~clk), .ENA(bae[0]), .SSRA(1'b0), .ADDRA(buffer_addr[12:3]), .WEA(we), .DIA(wdBus[3:0]),
.CLKB(~clk), .ENB(en_ev), .SSRB(1'b0), .ADDRB(evalfit_addr), .WEB(we_eval),.DIB(ev_do[3:0]), .DOB(ev_di[3:0])); //D3-D0
RAMB16_S4_S4 ba1( .CLKA(~clk), .ENA(bae[0]), .SSRA(1'b0), .ADDRA(buffer_addr[12:3]), .WEA(we), .DIA(wdBus[7:4]),
.CLKB(~clk), .ENB(en_ev), .SSRB(1'b0), .ADDRB(evalfit_addr), .WEB(we_eval),.DIB(ev_do[7:4]), .DOB(ev_di[7:4])); //D7-D4
assign address[4:0] = buffer_addr[4:0];
assign enReg = buffer_addr[12];
RAMB16_S4_S4 ba2( .CLKA(~clk), .ENA(bae[1]), .SSRA(1'b0), .ADDRA(buffer_addr[12:3]), .WEA(we), .DIA(wdBus[3:0]),
.CLKB(~clk), .ENB(en_ev), .SSRB(1'b0), .ADDRB(evalfit_addr), .WEB(we_eval),.DIB(ev_do[11:8]), .DOB(ev_di[11:8])); //D11-D8
RAMB16_S4_S4 ba3( .CLKA(~clk), .ENA(bae[1]), .SSRA(1'b0), .ADDRA(buffer_addr[12:3]), .WEA(we), .DIA(wdBus[7:4]),
.CLKB(~clk), .ENB(en_ev), .SSRB(1'b0), .ADDRB(evalfit_addr), .WEB(we_eval),.DIB(ev_do[15:12]), .DOB(ev_di[15:12]));//D15-D12
assign reg0[7:0] = reg_bank[0];
assign reg0[15:8] = reg_bank[1];
assign reg0[23:16] = reg_bank[2];
assign reg0[31:24] = reg_bank[3];
assign reg1[7:0] = reg_bank[4];
assign reg1[15:8] = reg_bank[5];
assign reg1[23:16] = reg_bank[6];
assign reg1[31:24] = reg_bank[7];
assign reg2[7:0] = reg_bank[8];
assign reg2[15:8] = reg_bank[9];
assign reg2[23:16] = reg_bank[10];
assign reg2[31:24] = reg_bank[11];
assign reg3[7:0] = reg_bank[12];
assign reg3[15:8] = reg_bank[13];
assign reg3[23:16] = reg_bank[14];
assign reg3[31:24] = reg_bank[15];
assign reg4[7:0] = reg_bank[16];
assign reg4[15:8] = reg_bank[17];
assign reg4[23:16] = reg_bank[18];
assign reg4[31:24] = reg_bank[19];
RAMB16_S4_S4 ba4( .CLKA(~clk), .ENA(bae[2]), .SSRA(1'b0), .ADDRA(buffer_addr[12:3]), .WEA(we), .DIA(wdBus[3:0]),
.CLKB(~clk), .ENB(en_ev), .SSRB(1'b0), .ADDRB(evalfit_addr), .WEB(we_eval),.DIB(ev_do[19:16]), .DOB(ev_di[19:16])); //D19-D16
RAMB16_S4_S4 ba5( .CLKA(~clk), .ENA(bae[2]), .SSRA(1'b0), .ADDRA(buffer_addr[12:3]), .WEA(we), .DIA(wdBus[7:4]),
.CLKB(~clk), .ENB(en_ev), .SSRB(1'b0), .ADDRB(evalfit_addr), .WEB(we_eval),.DIB(ev_do[23:20]), .DOB(ev_di[23:20])); //D23-D20
assign max_lev = reg_bank[28];
assign control = reg_bank[29];
assign max_com[7:0] = reg_bank[30];
assign max_com[15:8] = reg_bank[31];
// Write control
always @(negedge clk)
if(we & enReg) begin
case (address)
0: reg_bank[0] = wdBus;
1: reg_bank[1] = wdBus;
2: reg_bank[2] = wdBus;
3: reg_bank[3] = wdBus;
4: reg_bank[4] = wdBus;
5: reg_bank[5] = wdBus;
6: reg_bank[6] = wdBus;
7: reg_bank[7] = wdBus;
8: reg_bank[8] = wdBus;
9: reg_bank[9] = wdBus;
10: reg_bank[10] = wdBus;
11: reg_bank[11] = wdBus;
12: reg_bank[12] = wdBus;
13: reg_bank[13] = wdBus;
14: reg_bank[14] = wdBus;
15: reg_bank[15] = wdBus;
16: reg_bank[16] = wdBus;
17: reg_bank[17] = wdBus;
18: reg_bank[18] = wdBus;
19: reg_bank[19] = wdBus;
28: reg_bank[28] = wdBus;
29: reg_bank[29] = wdBus;
30: reg_bank[30] = wdBus;
31: reg_bank[31] = wdBus;
endcase
end
RAMB16_S4_S4 ba6( .CLKA(~clk), .ENA(bae[3]), .SSRA(1'b0), .ADDRA(buffer_addr[12:3]), .WEA(we), .DIA(wdBus[3:0]),
.CLKB(~clk), .ENB(en_ev), .SSRB(1'b0), .ADDRB(evalfit_addr), .WEB(we_eval),.DIB(ev_do[27:24]), .DOB(ev_di[27:24])); //D27-D24
RAMB16_S4_S4 ba7( .CLKA(~clk), .ENA(bae[3]), .SSRA(1'b0), .ADDRA(buffer_addr[12:3]), .WEA(we), .DIA(wdBus[7:4]),
.CLKB(~clk), .ENB(en_ev), .SSRB(1'b0), .ADDRB(evalfit_addr), .WEB(we_eval),.DIB(ev_do[31:28]), .DOB(ev_di[31:28])); //D31-D28
RAMB16_S36_S36 #(.INIT_00(256'hABCDEF00_00000000_00000000_00000000_00000000_00000000_00000000_76543210) )
mem0 ( .CLKA(~clk), .ENA(en0), .SSRA(1'b0), .ADDRA(buffer_addr[11:3]), .WEA(we0), .DIA(DIA_Aux[31:0]), .DIPA(0'b0), .DOA(DOA_Aux[31:0]),
.CLKB(~clk), .ENB(en_ev), .SSRB(1'b0), .ADDRB(evalfit_addr), .WEB(we_eval), .DIB(ev_do[31:0]), .DIPB(0'b0), .DOB(ev_di[31:0]));
RAMB16_S36_S36 mem1( .CLKA(~clk), .ENA(en1), .SSRA(1'b0), .ADDRA(buffer_addr[11:3]), .WEA(we1), .DIA(DIA_Aux[31:0]), .DIPA(0'b0), .DOA(DOA_Aux[63:32]),
.CLKB(~clk), .ENB(en_ev),.SSRB(1'b0), .ADDRB(evalfit_addr), .WEB(we_eval), .DIB(ev_do[63:32]), .DIPB(0'b0), .DOB(ev_di[63:32]));
RAMB16_S4_S4 ba8( .CLKA(~clk), .ENA(bae[4]), .SSRA(1'b0), .ADDRA(buffer_addr[12:3]), .WEA(we), .DIA(wdBus[3:0]),
.CLKB(~clk), .ENB(en_ev), .SSRB(1'b0), .ADDRB(evalfit_addr), .WEB(we_eval),.DIB(ev_do[35:32]), .DOB(ev_di[35:32])); //D35-D32
RAMB16_S4_S4 ba9( .CLKA(~clk), .ENA(bae[4]), .SSRA(1'b0), .ADDRA(buffer_addr[12:3]), .WEA(we), .DIA(wdBus[7:4]),
.CLKB(~clk), .ENB(en_ev), .SSRB(1'b0), .ADDRB(evalfit_addr), .WEB(we_eval),.DIB(ev_do[39:36]), .DOB(ev_di[39:36])); //D39-D36
// evalfit_peripheral
evalfit_peripheral evalfit( .clk(clk), .reset(~reset), .habilita(control[0]), .maxcombs(max_com), .nivel_max(max_lev),
RAMB16_S4_S4 ba10(.CLKA(~clk), .ENA(bae[5]), .SSRA(1'b0), .ADDRA(buffer_addr[12:3]), .WEA(we), .DIA(wdBus[3:0]),
.CLKB(~clk), .ENB(en_ev), .SSRB(1'b0), .ADDRB(evalfit_addr), .WEB(we_eval),.DIB(ev_do[43:40]), .DOB(ev_di[43:40])); //D43-D40
RAMB16_S4_S4 ba11(.CLKA(~clk), .ENA(bae[5]), .SSRA(1'b0), .ADDRA(buffer_addr[12:3]), .WEA(we), .DIA(wdBus[7:4]),
.CLKB(~clk), .ENB(en_ev), .SSRB(1'b0), .ADDRB(evalfit_addr), .WEB(we_eval),.DIB(ev_do[47:44]), .DOB(ev_di[47:44])); //D47-D44
RAMB16_S4_S4 ba12(.CLKA(~clk), .ENA(bae[6]), .SSRA(1'b0), .ADDRA(buffer_addr[12:3]), .WEA(we), .DIA(wdBus[3:0]),
.CLKB(~clk), .ENB(en_ev), .SSRB(1'b0), .ADDRB(evalfit_addr), .WEB(we_eval),.DIB(ev_do[51:48]), .DOB(ev_di[51:48])); //D51-D48
RAMB16_S4_S4 ba13(.CLKA(~clk), .ENA(bae[6]), .SSRA(1'b0), .ADDRA(buffer_addr[12:3]), .WEA(we), .DIA(wdBus[7:4]),
.CLKB(~clk), .ENB(en_ev), .SSRB(1'b0), .ADDRB(evalfit_addr), .WEB(we_eval),.DIB(ev_do[55:52]), .DOB(ev_di[55:52])); //D55-D52
RAMB16_S4_S4 ba14(.CLKA(~clk), .ENA(bae[7]), .SSRA(1'b0), .ADDRA(buffer_addr[12:3]), .WEA(we), .DIA(wdBus[3:0]),
.CLKB(~clk), .ENB(en_ev), .SSRB(1'b0), .ADDRB(evalfit_addr), .WEB(we_eval),.DIB(ev_do[59:56]), .DOB(ev_di[59:56])); //D59-D56
RAMB16_S4_S4 ba15(.CLKA(~clk), .ENA(bae[7]), .SSRA(1'b0), .ADDRA(buffer_addr[12:3]), .WEA(we), .DIA(wdBus[7:4]),
.CLKB(~clk), .ENB(en_ev), .SSRB(1'b0), .ADDRB(evalfit_addr), .WEB(we_eval),.DIB(ev_do[63:60]), .DOB(ev_di[63:60])); //D63-D60
// evalfit_peripheral
evalfit_peripheral evalfit( .clk(clk), .reset(reset), .habilita(control[0]), .maxcombs(max_com), .nivel_max(max_lev),
.peripheral_mem_in(ev_di), .peripheral_mem_en(en_eval), .peripheral_mem_out(ev_do), .peripheral_mem_we(we_eval),
.peripheral_mem_addr(evalfit_addr), .evalfit3_estado(status), .errores(error),
.fin_ack(irq_pin), .reg0_s(reg0), .reg1_s(reg1), .reg2_s(reg2), .reg3_s(reg3), .reg4_s(reg4));
// MersenneTwister
mt_mem random( .clk(clk), .ena(1'b1), .resetn(reset), .random(mt_rnd));
reg_bank RegBank( .clk(clk), .reset(reset), .en(buffer_addr[12]), .we(we), .wdBus(wdBus), .rdBus(rdBus), .address(buffer_addr[4:0]),
.reg0(reg0), .reg1(reg1), .reg2(reg2), .reg3(reg3), .reg4(reg4), .error(error), .status(status),
.max_com(max_com), .max_lev(max_lev), .control(control));
// mt_mem
mt_mem random( .clk(clk), .ena(1'b1), .resetn(~reset), .random(mt_rnd));
endmodule

4
Examples/ehw4/logic/evalfit_peripheral.vhd
View File

@@ -25,9 +25,9 @@ entity evalfit_peripheral is
Port ( clk, reset, habilita: in STD_LOGIC;
maxcombs : in STD_LOGIC_VECTOR (0 to 15);
nivel_max : in STD_LOGIC_VECTOR (0 to 3);
peripheral_mem_in : in STD_LOGIC_VECTOR (0 to 63);
peripheral_mem_in : in STD_LOGIC_VECTOR (0 to 63);
peripheral_mem_en : out std_logic;
peripheral_mem_out : out STD_LOGIC_VECTOR (0 to 63);
peripheral_mem_out : out STD_LOGIC_VECTOR (0 to 63);
peripheral_mem_we : out STD_LOGIC;
peripheral_mem_addr : out STD_LOGIC_VECTOR (0 to 8);
evalfit3_estado : out std_logic_vector(0 to 7);