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Code

Adding write funtions to blink driver sample

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This commit is contained in:
Carlos Camargo 2010-05-04 11:17:38 -05:00
parent 07888ac4c4
commit de9acb468b
6 changed files with 79 additions and 142 deletions
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23
Examples/drivers/blink/blinker.c
View File

@ -61,12 +61,30 @@ static int device_open(struct inode *inode, struct file *file)
return SUCCESS; return SUCCESS;
} }
static ssize_t
device_write(struct file *filp, const char *buff, size_t count, loff_t * off)
{
const char cmd = buff[0];
if(cmd=='Q')
{
printk(KERN_INFO "Q...\n");
gpio_set_value(LED_PIN, 1);
}
else
if(cmd=='S'){
printk(KERN_INFO "S...\n");
gpio_set_value(LED_PIN, 0);
}
return 1;
}
static int device_release(struct inode *inode, struct file *file) static int device_release(struct inode *inode, struct file *file)
{ {
is_device_open = 0; is_device_open = 0;
gpio_set_value(LED_PIN, 0);
module_put(THIS_MODULE); module_put(THIS_MODULE);
printk( KERN_INFO "Close BLINKER\n" ); printk( KERN_INFO "Close BLINKER\n" );
@ -76,6 +94,7 @@ static int device_release(struct inode *inode, struct file *file)
struct file_operations fops = { struct file_operations fops = {
.open = device_open, .open = device_open,
.write = device_write,
.release = device_release, .release = device_release,
}; };

3
plasma/gpio/gpio.c
View File

@ -39,6 +39,9 @@ int main(void)
data16++; data16++;
*data32 = 0x30303030; *data32 = 0x30303030;
data32++;
*data32 = 0x31313131;
test8 = *data8; test8 = *data8;
test16 = *data16; test16 = *data16;

6
plasma/logic/Makefile
View File

@ -10,7 +10,7 @@ SIM_COMP_SCRIPT = simulation/$(DESIGN)_TB.do
#SIM_INIT_SCRIPT = simulation/$(DESIGN)_init.do #SIM_INIT_SCRIPT = simulation/$(DESIGN)_init.do
SIMGEN_OPTIONS = -p $(FPGA_ARCH) -lang $(LANGUAGE) SIMGEN_OPTIONS = -p $(FPGA_ARCH) -lang $(LANGUAGE)
SRC_HDL = plasma.vhd alu.vhd control.vhd mem_ctrl.vhd mult.vhd shifter.vhd bus_mux.vhd ddr_ctrl.vhd mlite_cpu.vhd pc_next.vhd cache.vhd eth_dma.vhd mlite_pack.vhd pipeline.vhd reg_bank.vhd uart.vhd plasma_3e.vhd ram_image.vhd SRC_HDL = plasma.vhd alu.vhd control.vhd mem_ctrl.vhd mult.vhd shifter.vhd bus_mux.vhd ddr_ctrl.vhd mlite_cpu.vhd pc_next.vhd cache.vhd eth_dma.vhd mlite_pack.vhd pipeline.vhd reg_bank.vhd uart.vhd ram_image.vhd
all: bits all: bits
@ -53,8 +53,8 @@ build/project.xst: build/project.src
build/project.ngc: build/project.xst $(SRC) build/project.ngc: build/project.xst $(SRC)
cd build && xst -ifn project.xst -ofn project.log cd build && xst -ifn project.xst -ofn project.log
build/project.ngd: build/project.ngc $(PINS) build/project.ngd: build/project.ngc #$(PINS)
cd build && ngdbuild -p $(DEVICE) project.ngc -uc ../$(PINS) cd build && ngdbuild -p $(DEVICE) project.ngc #-uc ../$(PINS)
build/project.ncd: build/project.ngd build/project.ncd: build/project.ngd
cd build && map -pr b -p $(DEVICE) project cd build && map -pr b -p $(DEVICE) project

12
plasma/logic/mlite_pack.vhd
View File

@ -414,21 +414,15 @@ package mlite_pack is
component plasma component plasma
generic(memory_type : string := "XILINX_X16"; --"DUAL_PORT_" "ALTERA_LPM"; generic(memory_type : string := "XILINX_X16"; --"DUAL_PORT_" "ALTERA_LPM";
log_file : string := "UNUSED"; log_file : string := "UNUSED");
use_cache : std_logic := '0');
port(clk : in std_logic; port(clk : in std_logic;
reset : in std_logic; reset : in std_logic;
uart_write : out std_logic; uart_write : out std_logic;
uart_read : in std_logic; uart_read : in std_logic;
address : out std_logic_vector(31 downto 2);
byte_we : out std_logic_vector(3 downto 0);
data_write : out std_logic_vector(31 downto 0);
data_read : in std_logic_vector(31 downto 0); data_read : in std_logic_vector(31 downto 0);
mem_pause_in : in std_logic; mem_pause_in : in std_logic
);
gpio0_out : out std_logic_vector(31 downto 0);
gpioA_in : in std_logic_vector(31 downto 0));
end component; --plasma end component; --plasma
component ddr_ctrl component ddr_ctrl

133
plasma/logic/plasma.vhd
View File

@ -20,14 +20,6 @@
-- 0x20000030 GPIO0 Out Set bits -- 0x20000030 GPIO0 Out Set bits
-- 0x20000040 GPIO0 Out Clear bits -- 0x20000040 GPIO0 Out Clear bits
-- 0x20000050 GPIOA In -- 0x20000050 GPIOA In
-- 0x20000060 Counter
-- IRQ bits:
-- 7 GPIO31
-- 6 ^GPIO31
-- 3 Counter(18)
-- 2 ^Counter(18)
-- 1 ^UartWriteBusy
-- 0 UartDataAvailable
--------------------------------------------------------------------- ---------------------------------------------------------------------
library ieee; library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_1164.all;
@ -35,21 +27,16 @@ use work.mlite_pack.all;
entity plasma is entity plasma is
generic(memory_type : string := "XILINX_16X"; --"DUAL_PORT_" "ALTERA_LPM"; generic(memory_type : string := "XILINX_16X"; --"DUAL_PORT_" "ALTERA_LPM";
log_file : string := "UNUSED"; log_file : string := "UNUSED");
use_cache : std_logic := '0');
port(clk : in std_logic; port(clk : in std_logic;
reset : in std_logic; reset : in std_logic;
uart_write : out std_logic; uart_write : out std_logic;
uart_read : in std_logic; uart_read : in std_logic;
address : out std_logic_vector(31 downto 2);
byte_we : out std_logic_vector(3 downto 0);
data_write : out std_logic_vector(31 downto 0);
data_read : in std_logic_vector(31 downto 0); data_read : in std_logic_vector(31 downto 0);
mem_pause_in : in std_logic; mem_pause_in : in std_logic
gpio0_out : out std_logic_vector(31 downto 0); );
gpioA_in : in std_logic_vector(31 downto 0));
end; --entity plasma end; --entity plasma
architecture logic of plasma is architecture logic of plasma is
@ -70,13 +57,11 @@ architecture logic of plasma is
signal enable_uart_read : std_logic; signal enable_uart_read : std_logic;
signal enable_uart_write : std_logic; signal enable_uart_write : std_logic;
signal gpio0_reg : std_logic_vector(31 downto 0);
signal uart_write_busy : std_logic; signal uart_write_busy : std_logic;
signal uart_data_avail : std_logic; signal uart_data_avail : std_logic;
signal irq_mask_reg : std_logic_vector(7 downto 0); signal irq_mask_reg : std_logic_vector(7 downto 0);
signal irq_status : std_logic_vector(7 downto 0); signal irq_status : std_logic_vector(7 downto 0);
signal irq : std_logic; signal irq : std_logic;
signal counter_reg : std_logic_vector(31 downto 0);
signal ram_enable : std_logic; signal ram_enable : std_logic;
signal ram_byte_we : std_logic_vector(3 downto 0); signal ram_byte_we : std_logic_vector(3 downto 0);
@ -84,27 +69,10 @@ architecture logic of plasma is
signal ram_data_w : std_logic_vector(31 downto 0); signal ram_data_w : std_logic_vector(31 downto 0);
signal ram_data_r : std_logic_vector(31 downto 0); signal ram_data_r : std_logic_vector(31 downto 0);
signal cache_check : std_logic;
signal cache_checking : std_logic;
signal cache_miss : std_logic;
signal cache_hit : std_logic;
begin --architecture begin --architecture
write_enable <= '1' when cpu_byte_we /= "0000" else '0'; --%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
mem_busy <= mem_pause_in; -- PROCESSOR
cache_hit <= cache_checking and not cache_miss; --%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
cpu_pause <= '0'; --(uart_write_busy and enable_uart and write_enable) or --UART busy
-- cache_miss or --Cache wait
-- (cpu_address(28) and not cache_hit and mem_busy); --DDR or flash
-- gpio0_out(31 downto 29) <= gpio0_reg(31 downto 29);
-- gpio0_out(23 downto 0) <= gpio0_reg(23 downto 0);
enable_misc <= '1' when cpu_address(30 downto 28) = "010" else '0';
enable_uart <= '1' when enable_misc = '1' and cpu_address(7 downto 4) = "0000" else '0';
enable_uart_read <= enable_uart and not write_enable;
enable_uart_write <= enable_uart and write_enable;
cpu_address(1 downto 0) <= "00";
u1_cpu: mlite_cpu u1_cpu: mlite_cpu
generic map (memory_type => memory_type) generic map (memory_type => memory_type)
PORT MAP ( PORT MAP (
@ -121,45 +89,35 @@ begin --architecture
data_r => cpu_data_r, data_r => cpu_data_r,
mem_pause => cpu_pause); mem_pause => cpu_pause);
opt_cache: if use_cache = '0' generate --%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
cache_check <= '0'; -- ADDRESS DECODER
cache_checking <= '0'; --%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
cache_miss <= '0'; write_enable <= '1' when cpu_byte_we /= "0000" else '0';
end generate; mem_busy <= mem_pause_in;
cpu_pause <= '0'; --(uart_write_busy and enable_uart and write_enable) or --UART busy
opt_cache2: if use_cache = '1' generate -- (cpu_address(28) and mem_busy); --DDR or flash
--Control 4KB unified cache that uses the upper 4KB of the 8KB
--internal RAM. Only lowest 2MB of DDR is cached. enable_uart <= '1' when cpu_address(30 downto 28) = "010" and cpu_address(7 downto 4) = "0000" else '0';
u_cache: cache enable_uart_read <= enable_uart and not write_enable;
generic map (memory_type => memory_type) enable_uart_write <= enable_uart and write_enable;
PORT MAP ( cpu_address(1 downto 0) <= "00";
clk => clk, ram_enable <= '1' when address_next(30 downto 28) = "000" else '0';
reset => reset, ram_byte_we <= byte_we_next;
address_next => address_next, ram_address(31 downto 13) <= ZERO(31 downto 13);
byte_we_next => byte_we_next, ram_address(12 downto 2) <= (address_next(12)) & address_next(11 downto 2);
cpu_address => cpu_address(31 downto 2), ram_data_w <= cpu_data_w;
mem_busy => mem_busy,
cache_check => cache_check, --Stage1: address_next in first 2MB DDR
cache_checking => cache_checking, --Stage2
cache_miss => cache_miss); --Stage3
end generate; --opt_cache2
misc_proc: process(clk, reset, cpu_address, enable_misc, misc_proc: process(clk, reset, cpu_address, enable_misc,
ram_data_r, data_read, data_read_uart, cpu_pause, ram_data_r, data_read, data_read_uart, cpu_pause,
irq_mask_reg, irq_status, gpio0_reg, write_enable, irq_mask_reg, irq_status, write_enable,
cache_checking, cpu_data_w)
gpioA_in, counter_reg, cpu_data_w)
begin begin
case cpu_address(30 downto 28) is case cpu_address(30 downto 28) is
when "000" => --internal RAM when "000" => --internal RAM
cpu_data_r <= ram_data_r; cpu_data_r <= ram_data_r;
when "001" => --external RAM when "001" => --external RAM
if cache_checking = '1' then
cpu_data_r <= ram_data_r; --cache
else
cpu_data_r <= data_read; --DDR cpu_data_r <= data_read; --DDR
end if;
when "010" => --misc when "010" => --misc
case cpu_address(6 downto 4) is case cpu_address(6 downto 4) is
when "000" => --uart when "000" => --uart
@ -168,48 +126,15 @@ begin --architecture
cpu_data_r <= ZERO(31 downto 8) & irq_mask_reg; cpu_data_r <= ZERO(31 downto 8) & irq_mask_reg;
when "010" => --irq_status when "010" => --irq_status
cpu_data_r <= ZERO(31 downto 8) & irq_status; cpu_data_r <= ZERO(31 downto 8) & irq_status;
when "011" => --gpio0
cpu_data_r <= gpio0_reg;
when "101" => --gpioA
cpu_data_r <= gpioA_in;
when "110" => --counter
cpu_data_r <= counter_reg;
when others => when others =>
cpu_data_r <= gpioA_in; cpu_data_r <= ZERO(31 downto 8) & data_read_uart;
end case; end case;
when "011" => --flash when "011" => --flash
cpu_data_r <= data_read; cpu_data_r <= data_read;
when others => when others =>
cpu_data_r <= ZERO; cpu_data_r <= ZERO;
end case; end case;
end process;
if reset = '1' then
irq_mask_reg <= ZERO(7 downto 0);
gpio0_reg <= ZERO;
counter_reg <= ZERO;
elsif rising_edge(clk) then
if cpu_pause = '0' then
if enable_misc = '1' and write_enable = '1' then
if cpu_address(6 downto 4) = "001" then
irq_mask_reg <= cpu_data_w(7 downto 0);
elsif cpu_address(6 downto 4) = "011" then
gpio0_reg <= gpio0_reg or cpu_data_w;
elsif cpu_address(6 downto 4) = "100" then
gpio0_reg <= gpio0_reg and not cpu_data_w;
end if;
end if;
end if;
counter_reg <= bv_inc(counter_reg);
end if;
end process;
ram_enable <= '1' when address_next(30 downto 28) = "000" or cache_check = '1' or cache_miss = '1' else '0';
ram_byte_we <= byte_we_next when cache_miss = '0' else "1111";
ram_address(31 downto 13) <= ZERO(31 downto 13);
ram_address(12 downto 2) <= (address_next(12) or cache_check) & address_next(11 downto 2)
when cache_miss = '0' else
'1' & cpu_address(11 downto 2); --Update cache after cache miss
ram_data_w <= cpu_data_w when cache_miss = '0' else data_read;
u2_ram: ram u2_ram: ram
generic map (memory_type => memory_type) generic map (memory_type => memory_type)
@ -235,10 +160,6 @@ begin --architecture
busy_write => uart_write_busy, busy_write => uart_write_busy,
data_avail => uart_data_avail); data_avail => uart_data_avail);
address <= cpu_address(31 downto 2);
byte_we <= cpu_byte_we;
data_write <= cpu_data_w;
gpio0_out(28 downto 24) <= ZERO(28 downto 24);
end; --architecture logic end; --architecture logic

44
plasma/logic/ram_image.vhd
View File

@ -45,11 +45,11 @@ INIT_00 => X"afafafafafafafafafafafafafafafaf2308000c241400ac273c243c243c273c",
INIT_01 => X"8f8f8f8f8f8f8f8f8f8f8f8f8f8f8f8f8f230c008c8c3caf00af00af2340afaf", INIT_01 => X"8f8f8f8f8f8f8f8f8f8f8f8f8f8f8f8f8f230c008c8c3caf00af00af2340afaf",
INIT_02 => X"acacacac0003373cac038cac8cac8cac8c243c40034040033423038f038f8f8f", INIT_02 => X"acacacac0003373cac038cac8cac8cac8c243c40034040033423038f038f8f8f",
INIT_03 => X"000300ac0300000034038c8c8c8c8c8c8c8c8c8c8c8c3403acacacacacacacac", INIT_03 => X"000300ac0300000034038c8c8c8c8c8c8c8c8c8c8c8c3403acacacacacacacac",
INIT_04 => X"913434ada5342434343ca5a5242434a134a1242434a034a024243434a024343c", INIT_04 => X"ad343434343c3ca5a5242434a534a1242434a134a0242434a034a0242434343c",
INIT_05 => X"240800100080afafaf270003ac001030008c343c0003ac8c34943c908d349434", INIT_05 => X"0080afafaf270003ac001030008c343c0003ac8c34943c908d349434913434ad",
INIT_06 => X"2400afafafaf272703008f8f8f00140082000c2682000c241400100082260c00", INIT_06 => X"afaf272703008f8f8f00140082000c2682000c241400100082260c0024080010",
INIT_07 => X"8f8c3c10000caf2730038c343c240827038f8f8f8f0216260c2424142c300224", INIT_07 => X"000caf2730038c343c240827038f8f8f8f0216260c2424142c3002242400afaf",
INIT_08 => X"00000000000000000000000000000024038c0014ac00248c3c24243c3c270300", INIT_08 => X"000000000000000000000024038c0014ac00248c3c24243c3c2703008f8c3c10",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
@ -122,11 +122,11 @@ INIT_00 => X"b8afaeadacabaaa9a8a7a6a5a4a3a2a1bd000000a560a4a0bd1d8404a5059c1c",
INIT_01 => X"b9b8afaeadacabaaa9a8a7a6a5a4a3a2a1a50086c6c406bb00bb00ba5a1abfb9", INIT_01 => X"b9b8afaeadacabaaa9a8a7a6a5a4a3a2a1a50086c6c406bb00bb00ba5a1abfb9",
INIT_02 => X"9392919000405a1a06e0a606a606a606a6a50584e0029b401bbd60bb60bbbabf", INIT_02 => X"9392919000405a1a06e0a606a606a606a6a50584e0029b401bbd60bb60bbbabf",
INIT_03 => X"00e000c4e0000085a2e09f9d9c9e979695949392919002e09f9d9c9e97969594", INIT_03 => X"00e000c4e0000085a2e09f9d9c9e979695949392919002e09f9d9c9e97969594",
INIT_04 => X"868283a26342038b8d02422302038a828903020388e28cc302038786a2028504", INIT_04 => X"8263428c8e0302634203028b238aa2030289038de2030288c387a20302868504",
INIT_05 => X"110080400082b1bfb0bd00e0a40040420062a30500e0a2a342860262a6844785", INIT_05 => X"0082b1bfb0bd00e0a40040420062a30500e0a2a342860262c6844785a68382c3",
INIT_06 => X"1080bfb0b1b2bdbde000b0b1bf00400002400010020000045100400002100040", INIT_06 => X"b1b2bdbde000b0b1bf0040000240001002000004510040000210004011008040",
INIT_07 => X"bf6203400000bfbd42e06263030400bde0b0b1b2bf1211100064644062431211", INIT_07 => X"0000bfbd42e06263030400bde0b0b1b2bf12111000646440624312111080bfb0",
INIT_08 => X"00000000000000040000802400800042e0a20083404584820563440302bde000", INIT_08 => X"000000040000802400800042e0a20083404584820563440302bde000bf620340",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
@ -199,11 +199,11 @@ INIT_00 => X"00000000000000000000000000000000ff00000000ff18000600060004008400",
INIT_01 => X"000000000000000000000000000000000000002000002000d800d800ff700000", INIT_01 => X"000000000000000000000000000000000000002000002000d800d800ff700000",
INIT_02 => X"0000000000000010000000000000000000010060006060000000000000000000", INIT_02 => X"0000000000000010000000000000000000010060006060000000000000000000",
INIT_03 => X"0000000000201000000000000000000000000000000000000000000000000000", INIT_03 => X"0000000000201000000000000000000000000000000000000000000000000000",
INIT_04 => X"0020100000302220303000002120200020000000100010000000101000001020", INIT_04 => X"0031303030313000002221200020002000200010000000100010000000101020",
INIT_05 => X"000080000000000000ff00000010ff000000002010000000aa00aa0000200030", INIT_05 => X"0000000000ff00000010ff000000002010000000aa00aa000020003000102000",
INIT_06 => X"009000000000ff00001000000000ff000020000000000000ff00000000000020", INIT_06 => X"0000ff00001000000000ff000020000000000000ff0000000000002000008000",
INIT_07 => X"000020ff000000ff0000000020000000000000000010ffff00000000000010ff", INIT_07 => X"000000ff0000000020000000000000000010ffff00000000000010ff00900000",
INIT_08 => X"00000000000000200000002028000000000000ff001000001004040000000000", INIT_08 => X"000000200000002028000000000000ff001000001004040000000000000020ff",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
@ -272,15 +272,15 @@ INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000")
RAMB16_S9_inst3 : RAMB16_S9 RAMB16_S9_inst3 : RAMB16_S9
generic map ( generic map (
INIT_00 => X"4c4844403c3834302c2824201c181410980e008004fd2a005800700064006001", INIT_00 => X"4c4844403c3834302c2824201c181410980e008004fd2a006800800074007001",
INIT_01 => X"504c4844403c3834302c2824201c18141000f12410200060125c1058fc005450", INIT_01 => X"504c4844403c3834302c2824201c18141000f52410200060125c1058fc005450",
INIT_02 => X"0c08040000083c0048080c440840043c006000000800000801681360115c5854", INIT_02 => X"0c08040000083c0048080c440840043c006000000800000801681360115c5854",
INIT_03 => X"00080c000810121900082c2824201c1814100c08040000082c2824201c181410", INIT_03 => X"00080c000810121900082c2824201c1814100c08040000082c2824201c181410",
INIT_04 => X"0006080000302204003000002120020000001413030004001211020100100000", INIT_04 => X"0031300004313000002221040002002014000004001312030002001110010000",
INIT_05 => X"0ac721160000141810e000080021fc020000200021080000aa00aa0000080004", INIT_05 => X"0000141810e000080021fc020000200021080000aa00aa000008000800080600",
INIT_06 => X"1c211c101418e020082110141800f5000021ac010000ac0df8000d000001ac21", INIT_06 => X"1418e020082110141800f5000021b0010000b00df8000d000001b0210acb2116",
INIT_07 => X"100000fd00f310e8010800200049ac20081014181c06f8fcac5730020a0f06fc", INIT_07 => X"00f710e8010800200049b020081014181c06f8fcb05730020a0f06fc1c211c10",
INIT_08 => X"00000000000000001010200000207084080000fb002104000064440000180800", INIT_08 => X"000000001010200000207084080000fb002104000074540000180800100000fd",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",