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Code Activity

Remove RC Power On Reset Circuit (C8, C9, R8, R9)

Browse Source 
Change Y3 footprint
Change D10 footprint
Remove J18, Using J17 circuit for switch between USB and DC plug power supply, this remove the possibility that the USB host
will be connected to DC wall adapter.
Change L13 footprint
This commit is contained in:
Carlos Camargo
2010-07-28 09:22:40 -05:00
parent 5041c0eb60
commit ea03c86992
29 changed files with 60357 additions and 60887 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
plasma/logic/mlite_pack.vhd
View File

@@ -10,6 +10,7 @@
-- Data types, constants, and add functions needed for the Plasma CPU.
---------------------------------------------------------------------
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
package mlite_pack is
@@ -425,7 +426,7 @@ package mlite_pack is
nwe : in std_logic;
noe : in std_logic;
ncs : in std_logic;
irq_pin : in std_logic;
irq_pin : out std_logic;
led : out std_logic);
end component; --plasma

32
plasma/logic/plasma.vhd
View File

@@ -27,6 +27,7 @@
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mlite_pack.all;
entity plasma is
@@ -41,7 +42,7 @@ entity plasma is
nwe : in std_logic;
noe : in std_logic;
ncs : in std_logic;
irq_pin : in std_logic;
irq_pin : out std_logic;
led : out std_logic
);
end; --entity plasma
@@ -57,6 +58,8 @@ architecture logic of plasma is
signal cpu_data_r : std_logic_vector(31 downto 0);
signal cpu_pause : std_logic;
signal bus_dec : std_logic_vector(6 downto 0);
signal data_read_uart : std_logic_vector(7 downto 0);
signal data_read_pic : std_logic_vector(7 downto 0);
signal write_enable : std_logic;
@@ -89,6 +92,7 @@ begin
--%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
led <= not(rst_in);
reset <= not(rst_in);
irq_pin <= not(rst_in);
clk_div: process(reset, clk, clk_in)
begin
@@ -143,23 +147,21 @@ begin
--%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-- BUS MULTIPLEXOR
--%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
bus_mux: process (cpu_address, ram_data_r, data_read_uart, data_read_pic)
variable bus_dec : std_logic_vector(6 downto 0);
variable bus_dec : std_logic_vector(4 downto 0);
begin
bus_dec := cpu_address(30 downto 28) & cpu_address(7 downto 4);
-- if cpu_address(30 downto 28) = "000" then
-- cpu_data_r <= ram_data_r;
-- else
bus_dec := cpu_address(29) & cpu_address(7 downto 4);
case bus_dec is
when "000----" => cpu_data_r <= ram_data_r;
when "0100000" => cpu_data_r <= ZERO(31 downto 8) & data_read_uart;
when "0100001" => cpu_data_r <= ZERO(31 downto 8) & data_read_pic;
when "0100010" => cpu_data_r <= ZERO(31 downto 8) & data_read_pic;
when "0100011" => cpu_data_r <= ZERO;
when "0100100" => cpu_data_r <= ZERO;
when "0100101" => cpu_data_r <= ZERO;
when "0100110" => cpu_data_r <= ZERO;
when "00000" | "00001" | "00010" | "00011" | "00100" | "00101" | "00110" | "00111" |
"01000" | "01001" | "01010" | "01011" | "01100" | "01101" | "01110" | "01111"
=> cpu_data_r <= ram_data_r;
when "10000" => cpu_data_r <= ZERO(31 downto 8) & data_read_uart;
when "10001" => cpu_data_r <= ZERO(31 downto 8) & data_read_pic;
when "10010" => cpu_data_r <= ZERO(31 downto 8) & data_read_pic;
when "10011" => cpu_data_r <= ZERO;
when "10100" => cpu_data_r <= ZERO;
when "10101" => cpu_data_r <= ZERO;
when "10110" => cpu_data_r <= ZERO;
when others => cpu_data_r <= ZERO;
end case;
-- end if;

182
plasma/logic/ram_image.vhd
View File

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RAMB16_S9_inst2 : RAMB16_S9
generic map (
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