mirror of
git://projects.qi-hardware.com/nn-usb-fpga.git
synced 2024-12-12 22:03:45 +02:00
120 lines
3.7 KiB
Makefile
120 lines
3.7 KiB
Makefile
##########################################################
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### WARNING YOU MUST SET THE VARIABLE XILINX FIRST ##
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### /install_dir/Xilinx/10.1/ISE/
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##########################################################
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DESIGN = plasma
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PINS = $(DESIGN).ucf
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DEVICE = xc3s500e-VQ100-4
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BGFLAGS = -g TdoPin:PULLNONE -g DonePin:PULLUP \
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-g CRC:enable -g StartUpClk:CCLK
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SIM_CMD = /opt/cad/modeltech/bin/vsim
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SIM_COMP_SCRIPT = simulation/$(DESIGN)_TB.do
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SIMGEN_OPTIONS = -p $(FPGA_ARCH) -lang $(LANGUAGE)
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SIMTOP = $(DESIGN)_tb
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GHDL_SIM_OPT = --stop-time=1ms
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SIMDIR = simu
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GHDL_CMD = ghdl
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GHDL_SIMU_FLAGS = --ieee=synopsys -P$$XILINX/ghdl/unisim --warn-no-vital-generic
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GHDL_SYNTHESIS_FLAGS = --ieee=synopsys -P$$XILINX/ghdl/unisim --warn-no-vital-generic
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GHDL_PANDR_FLAGS = --ieee=synopsys -P$$XILINX/ghdl/simprim --warn-no-vital-generic
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VIEW_CMD = gtkwave
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TESTBENCH_FILE = $(DESIGN)_TB.vhd
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SYNT_TESTBENCH_FILE = $(DESIGN)_TB_syn.vhd
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SYNTHESIS_FILE = simu/$(DESIGN)_synt.vhd
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LIBRARY_FILE = mlite_pack.vhd
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SRC_HDL = mlite_pack.vhd plasma.vhd ram_image.vhd alu.vhd control.vhd mem_ctrl.vhd mult.vhd shifter.vhd bus_mux.vhd mlite_cpu.vhd pc_next.vhd pipeline.vhd reg_bank.vhd uart.vhd
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all: bits
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remake: clean-build all
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clean:
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rm -rf *~ */*~ a.out *.log *.key *.edf *.ps trace.dat
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rm -rf *.bit rm -rf simulation/work simulation/*wlf
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rm -rf simulation/transcript
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clean-build:
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rm -rf build
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cleanall: clean clean_ghdl
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rm -rf build work $(DESIGN).bit
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bits: $(DESIGN).bit
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#
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# Synthesis
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#
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build/project.src:
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@[ -d build ] || mkdir build
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@rm -f $@
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for i in $(SRC); do echo verilog work ../$$i >> $@; done
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for i in $(SRC_HDL); do echo VHDL work ../$$i >> $@; done
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build/project.xst: build/project.src
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echo "run" > $@
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echo "-top $(DESIGN) " >> $@
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echo "-p $(DEVICE)" >> $@
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echo "-opt_mode Area" >> $@
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echo "-opt_level 1" >> $@
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echo "-ifn project.src" >> $@
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echo "-ifmt mixed" >> $@
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echo "-ofn project.ngc" >> $@
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echo "-ofmt NGC" >> $@
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echo "-rtlview yes" >> $@
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build/project.ngc: build/project.xst $(SRC)
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cd build && xst -ifn project.xst -ofn project.log
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build/project.ngd: build/project.ngc $(PINS)
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cd build && ngdbuild -p $(DEVICE) project.ngc -uc ../$(PINS)
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build/project.ncd: build/project.ngd
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cd build && map -pr b -p $(DEVICE) project
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build/project_r.ncd: build/project.ncd
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cd build && par -w project project_r.ncd
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build/project_r.twr: build/project_r.ncd
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cd build && trce -v 25 project_r.ncd project.pcf
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$(DESIGN).bit: build/project_r.ncd build/project_r.twr
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cd build && bitgen project_r.ncd -l -w $(BGFLAGS)
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@mv -f build/project_r.bit $@
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build/project.vhd: build/project.ngc
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cd build && netgen -w -ofmt vhdl project.ngc project.vhd
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sim:
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cd simulation; $(SIM_CMD) -do $(DESIGN)_TB.do
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ghdl-simu : ghdl-compil ghdl-run ghdl-view
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ghdl-synthesis : ghdl-compil-synthesis ghdl-run ghdl-view
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ghdl-compil :
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mkdir -p simu
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$(GHDL_CMD) -i $(GHDL_SIMU_FLAGS) --workdir=simu --work=work $(TESTBENCH_FILE) $(LIBRARY_FILE) $(SRC_HDL)
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$(GHDL_CMD) -m $(GHDL_SIMU_FLAGS) -fexplicit --workdir=simu --work=work $(SIMTOP)
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@mv $(SIMTOP) simu/$(SIMTOP)
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ghdl-compil-synthesis: build/project.vhd
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mkdir -p simu
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cp build/project.vhd simu/$(DESIGN)_synt.vhd
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$(GHDL_CMD) -i $(GHDL_SYNTHESIS_FLAGS) --workdir=simu --work=work $(SYNT_TESTBENCH_FILE) $(SYNTHESIS_FILE)
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$(GHDL_CMD) -m $(GHDL_SYNTHESIS_FLAGS) --workdir=simu --work=work $(SIMTOP)
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@mv $(SIMTOP) simu/$(SIMTOP)
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ghdl-run :
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@$(SIMDIR)/$(SIMTOP) $(GHDL_SIM_OPT) --vcdgz=$(SIMDIR)/$(SIMTOP).vcdgz
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ghdl-view:
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gunzip --stdout $(SIMDIR)/$(SIMTOP).vcdgz | $(VIEW_CMD) --vcd
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clean_ghdl :
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$(GHDL_CMD) --clean --workdir=simu
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-rm -rf simu
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