Fixing some examples, adding scripts for compiling xilinx libs with ghdl
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m255
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13
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cModel Technology
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d/home/cain/Embedded/ingenic/sakc/nn-usb-fpga/Examples/sram/logic/simulation
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vglbl
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IT?5S;>bN`@zG_25]R_4A33
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VnN]4Gon>inod6>M^M2[SV1
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w1273510321
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Fglbl.v
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L0 5
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OE;L;6.0d;29
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r1
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31
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o+libext+.v
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vsram_bus
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I4L5C3LJ<U_bBN0U__mYo>0
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V7R>S0^PdJz?6eY;E[l1^E2
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w1273543761
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F../sram_bus.v
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L0 2
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OE;L;6.0d;29
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r1
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31
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o+libext+.v
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vsram_bus_TB
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IeNSImUgW[X4l`QoUVUKI`3
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V<VFiY^801Z<UUJ?^z?JM20
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w1273676679
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F../sram_bus_TB.v
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L0 3
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OE;L;6.0d;29
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r1
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31
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o+libext+.v
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nsram_bus_@t@b
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vsram_bus_TB_v
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IA=m;kT@<eh:`ekMlOPXX@0
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VQ[@Nfjd=de;Dc[[gj0bf41
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w1273541944
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F../sram_bus_TB.v
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L0 3
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OE;L;6.0d;29
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r1
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31
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o+libext+.v
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nsram_bus_@t@b_v
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library verilog;
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use verilog.vl_types.all;
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entity glbl is
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generic(
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ROC_WIDTH : integer := 100000;
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TOC_WIDTH : integer := 0
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);
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end glbl;
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library verilog;
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use verilog.vl_types.all;
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entity sram_bus is
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generic(
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B : integer := 7
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);
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port(
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clk : in vl_logic;
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sram_data : inout vl_logic_vector;
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addr : in vl_logic_vector(12 downto 0);
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nwe : in vl_logic;
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ncs : in vl_logic;
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noe : in vl_logic;
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reset : in vl_logic;
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led : out vl_logic
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);
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end sram_bus;
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library verilog;
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use verilog.vl_types.all;
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entity sram_bus_TB_v is
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generic(
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PERIOD : integer := 20;
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DUTY_CYCLE : real := 0.500000;
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OFFSET : integer := 0;
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TSET : integer := 3;
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THLD : integer := 3;
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NWS : integer := 3;
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CAM_OFF : integer := 4000
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);
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end sram_bus_TB_v;
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/****************************************************************************************
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*
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* Disclaimer This software code and all associated documentation, comments or other
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* of Warranty: information (collectively "Software") is provided "AS IS" without
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* warranty of any kind. MICRON TECHNOLOGY, INC. ("MTI") EXPRESSLY
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* DISCLAIMS ALL WARRANTIES EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
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* TO, NONINFRINGEMENT OF THIRD PARTY RIGHTS, AND ANY IMPLIED WARRANTIES
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* OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. MTI DOES NOT
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* WARRANT THAT THE SOFTWARE WILL MEET YOUR REQUIREMENTS, OR THAT THE
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* OPERATION OF THE SOFTWARE WILL BE UNINTERRUPTED OR ERROR-FREE.
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* FURTHERMORE, MTI DOES NOT MAKE ANY REPRESENTATIONS REGARDING THE USE OR
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* THE RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS,
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* ACCURACY, RELIABILITY, OR OTHERWISE. THE ENTIRE RISK ARISING OUT OF USE
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* OR PERFORMANCE OF THE SOFTWARE REMAINS WITH YOU. IN NO EVENT SHALL MTI,
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* ITS AFFILIATED COMPANIES OR THEIR SUPPLIERS BE LIABLE FOR ANY DIRECT,
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* INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR SPECIAL DAMAGES (INCLUDING,
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* WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION,
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* OR LOSS OF INFORMATION) ARISING OUT OF YOUR USE OF OR INABILITY TO USE
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* THE SOFTWARE, EVEN IF MTI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH
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* DAMAGES. Because some jurisdictions prohibit the exclusion or
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* limitation of liability for consequential or incidental damages, the
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* above limitation may not apply to you.
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*
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* Copyright 2003 Micron Technology, Inc. All rights reserved.
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*
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****************************************************************************************/
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// Timing parameters based on Speed Grade
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// SYMBOL UNITS DESCRIPTION
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// ------ ----- -----------
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// `ifdef sg6T // Timing Parameters for -6T (CL = 2.5)
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parameter tCK = 6.0; // tCK ns Nominal Clock Cycle Time
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parameter tDQSQ = 0.45; // tDQSS ns DQS-DQ skew, DQS to last DQ valid, per group, per access
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parameter tMRD = 12.0; // tMRD ns Load Mode Register command cycle time
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parameter tRAP = 15.0; // tRAP ns ACTIVE to READ with Auto precharge command
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parameter tRAS = 42.0; // tRAS ns Active to Precharge command time
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parameter tRC = 60.0; // tRC ns Active to Active/Auto Refresh command time
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parameter tRFC = 120.0; // tRFC ns Refresh to Refresh Command interval time
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parameter tRCD = 15.0; // tRCD ns Active to Read/Write command time
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parameter tRP = 15.0; // tRP ns Precharge command period
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parameter tRRD = 12.0; // tRRD ns Active bank a to Active bank b command time
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parameter tWR = 15.0; // tWR ns Write recovery time
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// Size Parameters based on Part Width
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//`else `define x16
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parameter ADDR_BITS = 13; // Set this parameter to control how many Address bits are used
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parameter DQ_BITS = 16; // Set this parameter to control how many Data bits are used
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parameter DQS_BITS = 2; // Set this parameter to control how many DQS bits are used
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parameter DM_BITS = 2; // Set this parameter to control how many DM bits are used
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parameter COL_BITS = 10; // Set this parameter to control how many Column bits are used
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parameter full_mem_bits = 2+ADDR_BITS+COL_BITS; // Set this parameter to control how many unique addresses are used
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parameter part_mem_bits = 14; // Set this parameter to control how many unique addresses are used
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parameter no_halt = 0; // If set to 1, the model won't halt on command sequence/major errors
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parameter Debug = 1; // Turn on debug message
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///////////////////////////////////////////////////////////////////////////////
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// Copyright (c) 2005 Xilinx, Inc.
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// This design is confidential and proprietary of Xilinx, All Rights Reserved.
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///////////////////////////////////////////////////////////////////////////////
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// ____ ____
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// / /\/ /
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// /___/ \ / Vendor : Xilinx
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// \ \ \/ Version : $Name: mig_v1_73_b0 $
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// \ \ Application : MIG
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// / / Filename : mem_interface_top_parameters_0.v
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// /___/ /\ Date Last Modified : $Date: 2007/06/06 05:44:42 $
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// \ \ / \ Date Created : Mon May 2 2005
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// \___\/\___\
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// Device : Spartan-3/3E/3A
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// Design Name : DDR1 SDRAM
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// Purpose : This module has the parameters used in the design.
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///////////////////////////////////////////////////////////////////////////////
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`define data_width 16
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`define data_strobe_width 2
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`define data_mask_width 2
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`define clk_width 1
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`define fifo_16 1
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`define ReadEnable 1
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`define memory_width 8
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`define DatabitsPerReadClock 8
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`define DatabitsPerMask 8
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`define no_of_cs 1
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`define data_mask 1
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`define mask_disable 0
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`define RESET 0
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`define cke_width 1
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`define registered 0
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`define col_ap_width 11
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`define write_pipe_itr 1
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`define write_pipeline 4
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`define top_bottom 0
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`define left_right 1
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`define row_address 13
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`define column_address 10
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`define bank_address 2
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`define spartan3e 1
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`define burst_length 3'b001
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`define burst_type 1'b0
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`define cas_latency_value 3'b110
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`define Operating_mode 5'b00000
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`define load_mode_register 13'b0000001100001
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`define drive_strengh 1'b0
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`define dll_enable 1'b0
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`define ext_load_mode_register 13'b0000000000000
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`define chip_address 1
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`define reset_active_low 1'b1
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`define rcd_count_value 3'b001
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`define ras_count_value 4'b0101
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`define mrd_count_value 1'b0
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`define rp_count_value 3'b001
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`define rfc_count_value 6'b001001
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`define twr_count_value 3'b110
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`define twtr_count_value 3'b100
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`define max_ref_width 11
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`define max_ref_cnt 11'b10000000001
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`timescale 1ns/100ps
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********************************************************************************************
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The sim folder has sample test_bench files to simulate the designs in Modelsim environment.
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This folder has the memory model, test bench, glbl file and required parameter files.
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Read the steps in this file before simulations are done.
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To run simulations for this sample configuration, user has to generate the RTL from the tool for the following GUI
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options.
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Data_width : 64
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HDL : Verilog or VHDL
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Memory configuration : x16
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DIMM/Component : Component
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Memory Part No : MT46V16M16XX-5
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Add test bench : Yes
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Use DCM : Yes
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Number of controllers : 1
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Number of Write pipelines : 4
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-----------------------------------------------For Verilog or VHDL----------------------------------------------------------
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1. After the rtl is generated, create the Model sim project file. Add all the rtl files from the rtl folder
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to the project Also add the memory model, test bench and glbl files from the sim folder.
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2. Compile the design.
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3. After successful compilation of design load the design using the following comamnd.
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vsim -t ps +notimingchecks -L ../Modeltech_6.1a/unisims_ver work.ddr1_test_tb glbl
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Note : User should set proper path for unisim verilog libraries
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4. After the design is successfully loaded, run the simulations and view the waveforms.
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Notes :
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1. To run simulations for different data widths and configurations, users should modify the test bench files
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with right memory models and design files.
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2. User must manually change the frequency of the test bench for proper simulations.
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3. Users should modify the test bench files for without test bench case.
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//---------------------------------------------------------------------------
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// Behavioral model of a static ram chip
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//
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// Organization:
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//
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// 16 bit x 2**(adr_width-1)
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//---------------------------------------------------------------------------
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module sram16 #(
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parameter adr_width = 18
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) (
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input [adr_width-1:0] adr,
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inout [15:0] dat,
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input ub_n,
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input lb_n,
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input cs_n,
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input we_n,
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input oe_n
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);
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parameter dat_width = 16;
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//---------------------------------------------------------------------------
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// Actual RAM cells
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//---------------------------------------------------------------------------
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reg [7:0] mem_ub [0:1<<adr_width];
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reg [7:0] mem_lb [0:1<<adr_width];
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//---------------------------------------------------------------------------
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//
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//---------------------------------------------------------------------------
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wire [15:0] mem = { mem_ub[adr], mem_lb[adr] };
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wire [15:0] zzz = 16'bz;
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// Drive output
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assign dat = (!cs_n && !oe_n) ? mem : zzz;
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// Write to UB
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always @(*)
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if (!cs_n && !we_n && !ub_n)
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mem_ub[adr] = dat[15:8];
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// Write to LB
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always @(*)
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if (!cs_n && !we_n && !lb_n)
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mem_lb[adr] = dat[7:0];
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always @(*)
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if (!we_n && !oe_n)
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$display("Operational error in RamChip: OE and WE both active");
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endmodule
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// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/BUFG.v,v 1.5.158.1 2007/03/09 18:13:02 patrickp Exp $
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///////////////////////////////////////////////////////////////////////////////
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// Copyright (c) 1995/2004 Xilinx, Inc.
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// All Right Reserved.
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///////////////////////////////////////////////////////////////////////////////
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// ____ ____
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// / /\/ /
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// /___/ \ / Vendor : Xilinx
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// \ \ \/ Version : 8.1i (I.13)
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// \ \ Description : Xilinx Functional Simulation Library Component
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// / / Global Clock Buffer
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// /___/ /\ Filename : BUFG.v
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// \ \ / \ Timestamp : Thu Mar 25 16:42:14 PST 2004
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// \___\/\___\
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//
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// Revision:
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// 03/23/04 - Initial version.
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// End Revision
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`timescale 100 ps / 10 ps
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module BUFG (O, I);
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output O;
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input I;
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buf B1 (O, I);
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endmodule
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// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/FDDRRSE.v,v 1.15.48.1 2007/03/09 18:13:02 patrickp Exp $
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///////////////////////////////////////////////////////////////////////////////
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// Copyright (c) 1995/2004 Xilinx, Inc.
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// All Right Reserved.
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///////////////////////////////////////////////////////////////////////////////
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// ____ ____
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// / /\/ /
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// /___/ \ / Vendor : Xilinx
|
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// \ \ \/ Version : 8.1i (I.27)
|
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// \ \ Description : Xilinx Functional Simulation Library Component
|
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// / / Dual Data Rate D Flip-Flop with Synchronous Reset and Set and Clock Enable
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// /___/ /\ Filename : FDDRRSE.v
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// \ \ / \ Timestamp : Thu Mar 25 16:42:16 PST 2004
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// \___\/\___\
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//
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// Revision:
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// 03/23/04 - Initial version.
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// 02/04/05 - Rev 0.0.1 Remove input/output bufs; Seperate GSR from clock block.
|
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// 05/06/05 - Remove internal input data strobe and add to the output. (CR207678)
|
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// 10/20/05 - Add set & reset check to main block. (CR219794)
|
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// 10/28/05 - combine strobe block and data block. (CR220298).
|
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// 2/07/06 - Remove set & reset from main block and add specify block (CR225119)
|
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// 2/10/06 - Change Q from reg to wire (CR 225613)
|
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// End Revision
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`timescale 1 ps / 1 ps
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module FDDRRSE (Q, C0, C1, CE, D0, D1, R, S);
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parameter INIT = 1'h0;
|
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output Q;
|
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|
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input C0, C1, CE, D0, D1, R, S;
|
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wire Q;
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reg q_out;
|
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reg q0_out, q1_out;
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reg C0_tmp, C1_tmp;
|
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initial begin
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q_out = INIT;
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q0_out = INIT;
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q1_out = INIT;
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C0_tmp = 0;
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C1_tmp = 0;
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end
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assign Q = q_out;
|
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always @(posedge C0)
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if (CE == 1 || R == 1 || S == 1) begin
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C0_tmp <= 1;
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C0_tmp <= #100 0;
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end
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always @(posedge C1)
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if (CE == 1 || R == 1 || S == 1) begin
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C1_tmp <= 1;
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C1_tmp <= #100 0;
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end
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always @(posedge C0)
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if (R)
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q0_out <= 0;
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else if (S)
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q0_out <= 1;
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else if (CE)
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q0_out <= D0;
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always @(posedge C1)
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if (R)
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q1_out <= 0;
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else if (S)
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q1_out <= 1;
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else if (CE)
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q1_out <= D1;
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always @(posedge C0_tmp or posedge C1_tmp )
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if (C1_tmp)
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q_out = q1_out;
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else
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q_out = q0_out;
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specify
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if (R)
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(posedge C0 => (Q +: 1'b0)) = (100, 100);
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if (!R && S)
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(posedge C0 => (Q +: 1'b1)) = (100, 100);
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if (!R && !S && CE)
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(posedge C0 => (Q +: D0)) = (100, 100);
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if (R)
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(posedge C1 => (Q +: 1'b0)) = (100, 100);
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if (!R && S)
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(posedge C1 => (Q +: 1'b1)) = (100, 100);
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if (!R && !S && CE)
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(posedge C1 => (Q +: D1)) = (100, 100);
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endspecify
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endmodule
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// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/RAMB16_S2.v,v 1.7.158.1 2007/03/09 18:13:18 patrickp Exp $
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
// Copyright (c) 1995/2005 Xilinx, Inc.
|
||||
// All Right Reserved.
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
// ____ ____
|
||||
// / /\/ /
|
||||
// /___/ \ / Vendor : Xilinx
|
||||
// \ \ \/ Version : 8.1i (I.13)
|
||||
// \ \ Description : Xilinx Functional Simulation Library Component
|
||||
// / / 16K-Bit Data and 2K-Bit Parity Single Port Block RAM
|
||||
// /___/ /\ Filename : RAMB16_S2.v
|
||||
// \ \ / \ Timestamp : Thu Mar 10 16:43:35 PST 2005
|
||||
// \___\/\___\
|
||||
//
|
||||
// Revision:
|
||||
// 03/23/04 - Initial version.
|
||||
// End Revision
|
||||
|
||||
`ifdef legacy_model
|
||||
|
||||
`timescale 1 ps / 1 ps
|
||||
|
||||
module RAMB16_S2 (DO, ADDR, CLK, DI, EN, SSR, WE);
|
||||
|
||||
parameter INIT = 2'h0;
|
||||
parameter SRVAL = 2'h0;
|
||||
parameter WRITE_MODE = "WRITE_FIRST";
|
||||
|
||||
parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
|
||||
output [1:0] DO;
|
||||
reg do0_out, do1_out;
|
||||
|
||||
input [12:0] ADDR;
|
||||
input [1:0] DI;
|
||||
input EN, CLK, WE, SSR;
|
||||
|
||||
reg [18431:0] mem;
|
||||
reg [8:0] count;
|
||||
reg [1:0] wr_mode;
|
||||
|
||||
wire [12:0] addr_int;
|
||||
wire [1:0] di_int;
|
||||
wire en_int, clk_int, we_int, ssr_int;
|
||||
|
||||
tri0 GSR = glbl.GSR;
|
||||
|
||||
always @(GSR)
|
||||
if (GSR) begin
|
||||
assign do0_out = INIT[0];
|
||||
assign do1_out = INIT[1];
|
||||
end
|
||||
else begin
|
||||
deassign do0_out;
|
||||
deassign do1_out;
|
||||
end
|
||||
|
||||
buf b_do_out0 (DO[0], do0_out);
|
||||
buf b_do_out1 (DO[1], do1_out);
|
||||
buf b_addr_0 (addr_int[0], ADDR[0]);
|
||||
buf b_addr_1 (addr_int[1], ADDR[1]);
|
||||
buf b_addr_2 (addr_int[2], ADDR[2]);
|
||||
buf b_addr_3 (addr_int[3], ADDR[3]);
|
||||
buf b_addr_4 (addr_int[4], ADDR[4]);
|
||||
buf b_addr_5 (addr_int[5], ADDR[5]);
|
||||
buf b_addr_6 (addr_int[6], ADDR[6]);
|
||||
buf b_addr_7 (addr_int[7], ADDR[7]);
|
||||
buf b_addr_8 (addr_int[8], ADDR[8]);
|
||||
buf b_addr_9 (addr_int[9], ADDR[9]);
|
||||
buf b_addr_10 (addr_int[10], ADDR[10]);
|
||||
buf b_addr_11 (addr_int[11], ADDR[11]);
|
||||
buf b_addr_12 (addr_int[12], ADDR[12]);
|
||||
buf b_di_0 (di_int[0], DI[0]);
|
||||
buf b_di_1 (di_int[1], DI[1]);
|
||||
buf b_en (en_int, EN);
|
||||
buf b_clk (clk_int, CLK);
|
||||
buf b_we (we_int, WE);
|
||||
buf b_ssr (ssr_int, SSR);
|
||||
|
||||
initial begin
|
||||
for (count = 0; count < 256; count = count + 1) begin
|
||||
mem[count] <= INIT_00[count];
|
||||
mem[256 * 1 + count] <= INIT_01[count];
|
||||
mem[256 * 2 + count] <= INIT_02[count];
|
||||
mem[256 * 3 + count] <= INIT_03[count];
|
||||
mem[256 * 4 + count] <= INIT_04[count];
|
||||
mem[256 * 5 + count] <= INIT_05[count];
|
||||
mem[256 * 6 + count] <= INIT_06[count];
|
||||
mem[256 * 7 + count] <= INIT_07[count];
|
||||
mem[256 * 8 + count] <= INIT_08[count];
|
||||
mem[256 * 9 + count] <= INIT_09[count];
|
||||
mem[256 * 10 + count] <= INIT_0A[count];
|
||||
mem[256 * 11 + count] <= INIT_0B[count];
|
||||
mem[256 * 12 + count] <= INIT_0C[count];
|
||||
mem[256 * 13 + count] <= INIT_0D[count];
|
||||
mem[256 * 14 + count] <= INIT_0E[count];
|
||||
mem[256 * 15 + count] <= INIT_0F[count];
|
||||
mem[256 * 16 + count] <= INIT_10[count];
|
||||
mem[256 * 17 + count] <= INIT_11[count];
|
||||
mem[256 * 18 + count] <= INIT_12[count];
|
||||
mem[256 * 19 + count] <= INIT_13[count];
|
||||
mem[256 * 20 + count] <= INIT_14[count];
|
||||
mem[256 * 21 + count] <= INIT_15[count];
|
||||
mem[256 * 22 + count] <= INIT_16[count];
|
||||
mem[256 * 23 + count] <= INIT_17[count];
|
||||
mem[256 * 24 + count] <= INIT_18[count];
|
||||
mem[256 * 25 + count] <= INIT_19[count];
|
||||
mem[256 * 26 + count] <= INIT_1A[count];
|
||||
mem[256 * 27 + count] <= INIT_1B[count];
|
||||
mem[256 * 28 + count] <= INIT_1C[count];
|
||||
mem[256 * 29 + count] <= INIT_1D[count];
|
||||
mem[256 * 30 + count] <= INIT_1E[count];
|
||||
mem[256 * 31 + count] <= INIT_1F[count];
|
||||
mem[256 * 32 + count] <= INIT_20[count];
|
||||
mem[256 * 33 + count] <= INIT_21[count];
|
||||
mem[256 * 34 + count] <= INIT_22[count];
|
||||
mem[256 * 35 + count] <= INIT_23[count];
|
||||
mem[256 * 36 + count] <= INIT_24[count];
|
||||
mem[256 * 37 + count] <= INIT_25[count];
|
||||
mem[256 * 38 + count] <= INIT_26[count];
|
||||
mem[256 * 39 + count] <= INIT_27[count];
|
||||
mem[256 * 40 + count] <= INIT_28[count];
|
||||
mem[256 * 41 + count] <= INIT_29[count];
|
||||
mem[256 * 42 + count] <= INIT_2A[count];
|
||||
mem[256 * 43 + count] <= INIT_2B[count];
|
||||
mem[256 * 44 + count] <= INIT_2C[count];
|
||||
mem[256 * 45 + count] <= INIT_2D[count];
|
||||
mem[256 * 46 + count] <= INIT_2E[count];
|
||||
mem[256 * 47 + count] <= INIT_2F[count];
|
||||
mem[256 * 48 + count] <= INIT_30[count];
|
||||
mem[256 * 49 + count] <= INIT_31[count];
|
||||
mem[256 * 50 + count] <= INIT_32[count];
|
||||
mem[256 * 51 + count] <= INIT_33[count];
|
||||
mem[256 * 52 + count] <= INIT_34[count];
|
||||
mem[256 * 53 + count] <= INIT_35[count];
|
||||
mem[256 * 54 + count] <= INIT_36[count];
|
||||
mem[256 * 55 + count] <= INIT_37[count];
|
||||
mem[256 * 56 + count] <= INIT_38[count];
|
||||
mem[256 * 57 + count] <= INIT_39[count];
|
||||
mem[256 * 58 + count] <= INIT_3A[count];
|
||||
mem[256 * 59 + count] <= INIT_3B[count];
|
||||
mem[256 * 60 + count] <= INIT_3C[count];
|
||||
mem[256 * 61 + count] <= INIT_3D[count];
|
||||
mem[256 * 62 + count] <= INIT_3E[count];
|
||||
mem[256 * 63 + count] <= INIT_3F[count];
|
||||
end
|
||||
end
|
||||
|
||||
initial begin
|
||||
case (WRITE_MODE)
|
||||
"WRITE_FIRST" : wr_mode <= 2'b00;
|
||||
"READ_FIRST" : wr_mode <= 2'b01;
|
||||
"NO_CHANGE" : wr_mode <= 2'b10;
|
||||
default : begin
|
||||
$display("Attribute Syntax Error : The attribute WRITE_MODE on RAMB16_S2 instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE);
|
||||
$finish;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
|
||||
always @(posedge clk_int) begin
|
||||
if (en_int == 1'b1) begin
|
||||
if (ssr_int == 1'b1) begin
|
||||
do0_out <= SRVAL[0];
|
||||
do1_out <= SRVAL[1];
|
||||
end
|
||||
else begin
|
||||
if (we_int == 1'b1) begin
|
||||
if (wr_mode == 2'b00) begin
|
||||
do0_out <= di_int[0];
|
||||
do1_out <= di_int[1];
|
||||
end
|
||||
else if (wr_mode == 2'b01) begin
|
||||
do0_out <= mem[addr_int * 2 + 0];
|
||||
do1_out <= mem[addr_int * 2 + 1];
|
||||
end
|
||||
else begin
|
||||
do0_out <= do0_out;
|
||||
do1_out <= do1_out;
|
||||
end
|
||||
end
|
||||
else begin
|
||||
do0_out <= mem[addr_int * 2 + 0];
|
||||
do1_out <= mem[addr_int * 2 + 1];
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk_int) begin
|
||||
if (en_int == 1'b1 && we_int == 1'b1) begin
|
||||
mem[addr_int * 2 + 0] <= di_int[0];
|
||||
mem[addr_int * 2 + 1] <= di_int[1];
|
||||
end
|
||||
end
|
||||
|
||||
specify
|
||||
(CLK *> DO) = (100, 100);
|
||||
endspecify
|
||||
|
||||
endmodule
|
||||
|
||||
`else
|
||||
|
||||
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/RAMB16_S2.v,v 1.7.158.1 2007/03/09 18:13:18 patrickp Exp $
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
// Copyright (c) 1995/2005 Xilinx, Inc.
|
||||
// All Right Reserved.
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
// ____ ____
|
||||
// / /\/ /
|
||||
// /___/ \ / Vendor : Xilinx
|
||||
// \ \ \/ Version : 8.1i (I.13)
|
||||
// \ \ Description : Xilinx Timing Simulation Library Component
|
||||
// / / 16K-Bit Data and 2K-Bit Parity Single Port Block RAM
|
||||
// /___/ /\ Filename : RAMB16_S2.v
|
||||
// \ \ / \ Timestamp : Thu Mar 10 16:44:01 PST 2005
|
||||
// \___\/\___\
|
||||
//
|
||||
// Revision:
|
||||
// 03/23/04 - Initial version.
|
||||
// 03/10/05 - Initialized outputs.
|
||||
// End Revision
|
||||
|
||||
`timescale 1 ps/1 ps
|
||||
|
||||
module RAMB16_S2 (DO, ADDR, CLK, DI, EN, SSR, WE);
|
||||
|
||||
parameter INIT = 2'h0;
|
||||
parameter SRVAL = 2'h0;
|
||||
parameter WRITE_MODE = "WRITE_FIRST";
|
||||
|
||||
parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
|
||||
output [1:0] DO;
|
||||
|
||||
input [12:0] ADDR;
|
||||
input [1:0] DI;
|
||||
input EN, CLK, WE, SSR;
|
||||
|
||||
reg [1:0] do_out = INIT[1:0];
|
||||
|
||||
reg [1:0] mem [8191:0];
|
||||
|
||||
reg [8:0] count, countp;
|
||||
reg [1:0] wr_mode;
|
||||
|
||||
wire [12:0] addr_int;
|
||||
wire [1:0] di_int;
|
||||
wire en_int, clk_int, we_int, ssr_int;
|
||||
|
||||
wire di_enable = en_int && we_int;
|
||||
|
||||
tri0 GSR = glbl.GSR;
|
||||
wire gsr_int;
|
||||
|
||||
buf b_gsr (gsr_int, GSR);
|
||||
|
||||
buf b_do [1:0] (DO, do_out);
|
||||
buf b_addr [12:0] (addr_int, ADDR);
|
||||
buf b_di [1:0] (di_int, DI);
|
||||
buf b_en (en_int, EN);
|
||||
buf b_clk (clk_int, CLK);
|
||||
buf b_ssr (ssr_int, SSR);
|
||||
buf b_we (we_int, WE);
|
||||
|
||||
|
||||
always @(gsr_int)
|
||||
if (gsr_int) begin
|
||||
assign {do_out} = INIT;
|
||||
end
|
||||
else begin
|
||||
deassign do_out;
|
||||
end
|
||||
|
||||
|
||||
initial begin
|
||||
|
||||
for (count = 0; count < 128; count = count + 1) begin
|
||||
mem[count] = INIT_00[(count * 2) +: 2];
|
||||
mem[128 * 1 + count] = INIT_01[(count * 2) +: 2];
|
||||
mem[128 * 2 + count] = INIT_02[(count * 2) +: 2];
|
||||
mem[128 * 3 + count] = INIT_03[(count * 2) +: 2];
|
||||
mem[128 * 4 + count] = INIT_04[(count * 2) +: 2];
|
||||
mem[128 * 5 + count] = INIT_05[(count * 2) +: 2];
|
||||
mem[128 * 6 + count] = INIT_06[(count * 2) +: 2];
|
||||
mem[128 * 7 + count] = INIT_07[(count * 2) +: 2];
|
||||
mem[128 * 8 + count] = INIT_08[(count * 2) +: 2];
|
||||
mem[128 * 9 + count] = INIT_09[(count * 2) +: 2];
|
||||
mem[128 * 10 + count] = INIT_0A[(count * 2) +: 2];
|
||||
mem[128 * 11 + count] = INIT_0B[(count * 2) +: 2];
|
||||
mem[128 * 12 + count] = INIT_0C[(count * 2) +: 2];
|
||||
mem[128 * 13 + count] = INIT_0D[(count * 2) +: 2];
|
||||
mem[128 * 14 + count] = INIT_0E[(count * 2) +: 2];
|
||||
mem[128 * 15 + count] = INIT_0F[(count * 2) +: 2];
|
||||
mem[128 * 16 + count] = INIT_10[(count * 2) +: 2];
|
||||
mem[128 * 17 + count] = INIT_11[(count * 2) +: 2];
|
||||
mem[128 * 18 + count] = INIT_12[(count * 2) +: 2];
|
||||
mem[128 * 19 + count] = INIT_13[(count * 2) +: 2];
|
||||
mem[128 * 20 + count] = INIT_14[(count * 2) +: 2];
|
||||
mem[128 * 21 + count] = INIT_15[(count * 2) +: 2];
|
||||
mem[128 * 22 + count] = INIT_16[(count * 2) +: 2];
|
||||
mem[128 * 23 + count] = INIT_17[(count * 2) +: 2];
|
||||
mem[128 * 24 + count] = INIT_18[(count * 2) +: 2];
|
||||
mem[128 * 25 + count] = INIT_19[(count * 2) +: 2];
|
||||
mem[128 * 26 + count] = INIT_1A[(count * 2) +: 2];
|
||||
mem[128 * 27 + count] = INIT_1B[(count * 2) +: 2];
|
||||
mem[128 * 28 + count] = INIT_1C[(count * 2) +: 2];
|
||||
mem[128 * 29 + count] = INIT_1D[(count * 2) +: 2];
|
||||
mem[128 * 30 + count] = INIT_1E[(count * 2) +: 2];
|
||||
mem[128 * 31 + count] = INIT_1F[(count * 2) +: 2];
|
||||
mem[128 * 32 + count] = INIT_20[(count * 2) +: 2];
|
||||
mem[128 * 33 + count] = INIT_21[(count * 2) +: 2];
|
||||
mem[128 * 34 + count] = INIT_22[(count * 2) +: 2];
|
||||
mem[128 * 35 + count] = INIT_23[(count * 2) +: 2];
|
||||
mem[128 * 36 + count] = INIT_24[(count * 2) +: 2];
|
||||
mem[128 * 37 + count] = INIT_25[(count * 2) +: 2];
|
||||
mem[128 * 38 + count] = INIT_26[(count * 2) +: 2];
|
||||
mem[128 * 39 + count] = INIT_27[(count * 2) +: 2];
|
||||
mem[128 * 40 + count] = INIT_28[(count * 2) +: 2];
|
||||
mem[128 * 41 + count] = INIT_29[(count * 2) +: 2];
|
||||
mem[128 * 42 + count] = INIT_2A[(count * 2) +: 2];
|
||||
mem[128 * 43 + count] = INIT_2B[(count * 2) +: 2];
|
||||
mem[128 * 44 + count] = INIT_2C[(count * 2) +: 2];
|
||||
mem[128 * 45 + count] = INIT_2D[(count * 2) +: 2];
|
||||
mem[128 * 46 + count] = INIT_2E[(count * 2) +: 2];
|
||||
mem[128 * 47 + count] = INIT_2F[(count * 2) +: 2];
|
||||
mem[128 * 48 + count] = INIT_30[(count * 2) +: 2];
|
||||
mem[128 * 49 + count] = INIT_31[(count * 2) +: 2];
|
||||
mem[128 * 50 + count] = INIT_32[(count * 2) +: 2];
|
||||
mem[128 * 51 + count] = INIT_33[(count * 2) +: 2];
|
||||
mem[128 * 52 + count] = INIT_34[(count * 2) +: 2];
|
||||
mem[128 * 53 + count] = INIT_35[(count * 2) +: 2];
|
||||
mem[128 * 54 + count] = INIT_36[(count * 2) +: 2];
|
||||
mem[128 * 55 + count] = INIT_37[(count * 2) +: 2];
|
||||
mem[128 * 56 + count] = INIT_38[(count * 2) +: 2];
|
||||
mem[128 * 57 + count] = INIT_39[(count * 2) +: 2];
|
||||
mem[128 * 58 + count] = INIT_3A[(count * 2) +: 2];
|
||||
mem[128 * 59 + count] = INIT_3B[(count * 2) +: 2];
|
||||
mem[128 * 60 + count] = INIT_3C[(count * 2) +: 2];
|
||||
mem[128 * 61 + count] = INIT_3D[(count * 2) +: 2];
|
||||
mem[128 * 62 + count] = INIT_3E[(count * 2) +: 2];
|
||||
mem[128 * 63 + count] = INIT_3F[(count * 2) +: 2];
|
||||
end
|
||||
|
||||
end // initial begin
|
||||
|
||||
|
||||
initial begin
|
||||
case (WRITE_MODE)
|
||||
"WRITE_FIRST" : wr_mode <= 2'b00;
|
||||
"READ_FIRST" : wr_mode <= 2'b01;
|
||||
"NO_CHANGE" : wr_mode <= 2'b10;
|
||||
default : begin
|
||||
$display("Attribute Syntax Error : The Attribute WRITE_MODE on RAMB16_S2 instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE);
|
||||
$finish;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
|
||||
|
||||
always @(posedge clk_int) begin
|
||||
|
||||
if (en_int == 1'b1) begin
|
||||
|
||||
if (ssr_int == 1'b1) begin
|
||||
{do_out} <= #100 SRVAL;
|
||||
end
|
||||
else begin
|
||||
if (we_int == 1'b1) begin
|
||||
if (wr_mode == 2'b00) begin
|
||||
do_out <= #100 di_int;
|
||||
end
|
||||
else if (wr_mode == 2'b01) begin
|
||||
do_out <= #100 mem[addr_int];
|
||||
end
|
||||
end
|
||||
else begin
|
||||
do_out <= #100 mem[addr_int];
|
||||
end
|
||||
end
|
||||
|
||||
// memory
|
||||
if (we_int == 1'b1) begin
|
||||
mem[addr_int] <= di_int;
|
||||
end
|
||||
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
`endif
|
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
@ -0,0 +1,40 @@
|
|||
/*
|
||||
JZ47xx test gpio
|
||||
|
||||
Copyright (C) 2010 Andres Calderon andres.calderon@emqbit.com
|
||||
Carlos Camargo cicamargoba@unal.edu.co
|
||||
|
||||
This program is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 2 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
This program is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program; if not, write to the Free Software
|
||||
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */
|
||||
|
||||
#include <stdio.h>
|
||||
#include <unistd.h>
|
||||
|
||||
#include "jz47xx_gpio.h"
|
||||
|
||||
#define IRQ_PORT JZ_GPIO_PORT_C
|
||||
#define IRQ_PIN 15
|
||||
|
||||
int
|
||||
main ()
|
||||
{
|
||||
JZ_PIO *pio = jz_gpio_map (IRQ_PORT);
|
||||
|
||||
if (!pio)
|
||||
return -1;
|
||||
|
||||
jz_gpio_as_irq (pio, IRQ_PIN);
|
||||
|
||||
return 0;
|
||||
}
|
|
@ -23,12 +23,21 @@ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */
|
|||
|
||||
#include "jz47xx_gpio.h"
|
||||
|
||||
#define TEST_PORT JZ_GPIO_PORT_C
|
||||
#define TEST_PIN 17
|
||||
//#define TEST_PORT JZ_GPIO_PORT_C
|
||||
//#define TEST_PIN 17
|
||||
|
||||
int
|
||||
main ()
|
||||
main (int argc,char *argv[])
|
||||
|
||||
{
|
||||
int TEST_PORT, TEST_PIN;
|
||||
|
||||
if(argc != 3){
|
||||
fprintf(stderr,"\nUsage: %s TEST_PIN_PORT(A=0, B=1, C=2, D=3) TEST_PIN \n",argv[0]);
|
||||
}
|
||||
|
||||
TEST_PORT = ;
|
||||
TEST_PIN = ;
|
||||
JZ_PIO *pio = jz_gpio_map (TEST_PORT);
|
||||
|
||||
if (!pio)
|
|
@ -2,4 +2,4 @@
|
|||
/usr/bin/xc3sprog /root/binaries/ADC.bit
|
||||
/usr/bin/sgen -f 1000 &
|
||||
/root/binaries/ADC -qws -nomouse &
|
||||
|
||||
/root/binaries/enable_rx
|
||||
|
|
|
@ -1,44 +0,0 @@
|
|||
S00C0000696D6167652E62696E89
|
||||
S113000098000000D00000007801000038210000B2
|
||||
S1130010D0E10000F80000033400000034000000C8
|
||||
S1130020781C00003B9C0FFC781A00003B5A02A08D
|
||||
S11300307801000038210298780300003863029C9C
|
||||
S1130040442300045820000034210004E3FFFFFD92
|
||||
S1130050340100003402000034030000F800001DE5
|
||||
S113006034010001D0010000C3A000003401000FDE
|
||||
S1130070D0210000C3A0000034010000D001000022
|
||||
S1130080C3A00000C0200000E0000000379CFFF87F
|
||||
S11300905B8B00085B9D0004F80000573C2B0008B4
|
||||
S11300A0F8000055B56108003C2B0008F800005228
|
||||
S11300B0B56108003C2B0008F800004FB56108004A
|
||||
S11300C02B9D00042B8B0008379C0008C3A0000064
|
||||
S11300D0379CFFE45B8B001C5B8C00185B8D001469
|
||||
S11300E05B8E00105B8F000C5B9000085B9D00042E
|
||||
S11300F0F8000040340D00673401002A340E007506
|
||||
S1130100340F006478100000442D0008442E0016BB
|
||||
S1130110442F000ABA00080038210270F800004891
|
||||
S1130120F80000355C2DFFFAFBFFFFD9FBFFFFD67B
|
||||
S1130130F8000031E3FFFFFCFBFFFFD5B8205800B7
|
||||
S1130140FBFFFFD3B5616000516CFFF64161000015
|
||||
S1130150356B0001F8000031558BFFFDF8000026D7
|
||||
S1130160E3FFFFF1FBFFFFCAB8205800FBFFFFC805
|
||||
S1130170B5616000516CFFEBF800001F31610000B5
|
||||
S1130180356B0001558BFFFDF800001BE3FFFFE614
|
||||
S113019078020000384202903803C350284200001D
|
||||
S11301A0882308005841001034010000584100140D
|
||||
S11301B03401000A5841000C2841000C20210001A0
|
||||
S11301C04420FFFEC3A00000780100003821029003
|
||||
S11301D0282100003802C3505822000434020000D1
|
||||
S11301E0582200083402000E58220000C3A0000068
|
||||
S11301F0C3A00000780100003821028C28220000EE
|
||||
S113020028410000202100014420FFFE2841000471
|
||||
S1130210202100FFC3A00000780200003842028CB5
|
||||
S113022028430000202100FF286200002042001023
|
||||
S11302305C40FFFE58610004C3A00000402400009D
|
||||
S11302404480000B780200003842028C28430000EE
|
||||
S113025028620000204200105C40FFFE5864000445
|
||||
S113026034210001402400005C82FFFAC3A0000096
|
||||
S11302702A2A53414B432F626F6F746C6F6164651C
|
||||
S10F0280722A2A203E200D0A0000000013
|
||||
S10F028CF0000000F0010000F00200008F
|
||||
S9030000FC
|
|
@ -3,9 +3,6 @@
|
|||
#define MemoryRead(A) (*(volatile unsigned long*)(A))
|
||||
#define MemoryWrite(A,V) *(volatile unsigned long*)(A)=(V)
|
||||
|
||||
typedef unsigned long uint32;
|
||||
typedef unsigned short uint16;
|
||||
|
||||
|
||||
int main(void)
|
||||
{
|
||||
|
@ -13,23 +10,29 @@ int main(void)
|
|||
volatile unsigned short *data16;
|
||||
volatile unsigned int *data32;
|
||||
|
||||
|
||||
volatile unsigned char test8;
|
||||
volatile unsigned short test16;
|
||||
volatile unsigned int test32, tmp;
|
||||
volatile unsigned long test64;
|
||||
|
||||
/*
|
||||
Operaciones de acceso a memoria
|
||||
*/
|
||||
|
||||
data8 = (unsigned char *)(0x20000410);
|
||||
data16 = (unsigned short *)(0x20000210);
|
||||
data32 = (unsigned int *)(0x20000330);
|
||||
|
||||
*data8 = 0x10;
|
||||
*data8 = 0x44;
|
||||
data8++;
|
||||
*data8 = 0x66;
|
||||
data8++;
|
||||
*data8 = 0x55;
|
||||
data8++;
|
||||
*data8 = 0x22;
|
||||
data8++;
|
||||
*data8 = 0x11;
|
||||
data8++;
|
||||
*data8 = 0x12;
|
||||
data8++;
|
||||
*data8 = 0x13;
|
||||
data8++;
|
||||
*data8 = 0x14;
|
||||
|
||||
*data16 = 0x2020;
|
||||
data16++;
|
||||
|
@ -60,6 +63,25 @@ int main(void)
|
|||
data32 = (unsigned int *)(0x20000020);
|
||||
test32 = *data32;
|
||||
|
||||
|
||||
/*
|
||||
Operaciones aritméticas
|
||||
*/
|
||||
|
||||
|
||||
test32 = test32 + test8;
|
||||
test32 = 0x11111111 + test32;
|
||||
test32 = 0x1111 + test32;
|
||||
test32 = test32 + *data32;
|
||||
|
||||
test64 = test32 * test8;
|
||||
test64 = 0x11111111 * test32;
|
||||
test64 = 0x1111 * test32;
|
||||
test64 = test32 * *data32;
|
||||
|
||||
|
||||
|
||||
|
||||
while(1){
|
||||
|
||||
}
|
||||
|
|
|
@ -1,3 +1,7 @@
|
|||
##########################################################
|
||||
### WARNING YOU MUST SET THE VARIABLE XILINX FIRST ##
|
||||
### /install_dir/Xilinx/10.1/ISE/
|
||||
##########################################################
|
||||
DESIGN = plasma
|
||||
PINS = $(DESIGN).ucf
|
||||
DEVICE = xc3s500e-VQ100-4
|
||||
|
|
|
@ -47,12 +47,12 @@ INIT_02 => X"acacacac0003373cac038cac8cac8cac8c243c40034040033423038f038f8f8f",
|
|||
INIT_03 => X"000300ac0300000034038c8c8c8c8c8c8c8c8c8c8c8c3403acacacacacacacac",
|
||||
INIT_04 => X"3c34ac343c34a42434a42434a42434a02434a02434a02434a02434a024343c27",
|
||||
INIT_05 => X"8cac343caf008c34a730009434a330009034af008ca730009434a3300090ac34",
|
||||
INIT_06 => X"82240c00142400100080afafaf270003ac3c1030008c343c0008af008c34af00",
|
||||
INIT_07 => X"26240c2608240c00102c3002242400afafafaf2727038f8f8f0000140082260c",
|
||||
INIT_08 => X"2703008f8c3c10000caf2730038c343c2703008f240caf2727038f8f8f8f0216",
|
||||
INIT_09 => X"000000000000000000000000000000000024038c001424ac00008c243c3c243c",
|
||||
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_06 => X"008f300093af00008f8caf24008faf00343c8faf00008f300093af008c34af00",
|
||||
INIT_07 => X"30008c343c0008af0000008f8caf00000000008faf000000000000008faf0000",
|
||||
INIT_08 => X"2727038f8f8f0000140082260c82240c00142400100080afafaf270003ac3c10",
|
||||
INIT_09 => X"8f240caf2727038f8f8f8f021626240c2608240c00102c3002242400afafafaf",
|
||||
INIT_0A => X"8c001424ac00008c243c3c243c2703008f8c3c10000caf2730038c343c270300",
|
||||
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000002403",
|
||||
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
|
@ -122,14 +122,14 @@ INIT_00 => X"b8afaeadacabaaa9a8a7a6a5a4a3a2a1bd000000a560a4a0bd1d8404a5059c1c",
|
|||
INIT_01 => X"b9b8afaeadacabaaa9a8a7a6a5a4a3a2a1a50086c6c406bb00bb00ba5a1abfb9",
|
||||
INIT_02 => X"9392919000405a1a06e0a606a606a606a6a50584e0029b401bbd60bb60bbbabf",
|
||||
INIT_03 => X"00e000c4e0000085a2e09f9d9c9e979695949392919002e09f9d9c9e97969594",
|
||||
INIT_04 => X"026482420264820264820264820264a2026582026482026482026482026403bd",
|
||||
INIT_05 => X"62624202a2004262a242004262a242004262a20082a242004262a24200a28242",
|
||||
INIT_06 => X"04040000511180400082b0b1bfbd00e044024042006243020000a2006263a200",
|
||||
INIT_07 => X"108400100084000040824412111080b0b1b2bfbdbde0b0b1bf00004000021000",
|
||||
INIT_08 => X"bde000bf4202400000bfbd42e0424202bde000bf0400bfbdbde0b0b1b2bf1211",
|
||||
INIT_09 => X"000000000000000000040000802400800042e0a2006463404500624402054302",
|
||||
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_04 => X"028362420283620283620283620283a2028562028362028362028362028304bd",
|
||||
INIT_05 => X"82824202a2004282a242004282a242004282a20062a242004282a24200a26242",
|
||||
INIT_06 => X"00a34200a2a24300a382a24200a2a3624202a3a24300a34200a2a2008284a200",
|
||||
INIT_07 => X"42006243020000a2004300a382a24302430300a3a243024302430300a3a20043",
|
||||
INIT_08 => X"bdbde0b0b1bf0000400002100004040000511180400082b0b1bfbd00e0440240",
|
||||
INIT_09 => X"bf0400bfbdbde0b0b1b2bf1211108400100084000040824412111080b0b1b2bf",
|
||||
INIT_0A => X"a2006463404500624402054302bde000bf4202400000bfbd42e0424202bde000",
|
||||
INIT_0B => X"00000000000000000000000000000000000000000000040000802400800042e0",
|
||||
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
|
@ -195,18 +195,18 @@ INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000")
|
|||
|
||||
RAMB16_S9_inst2 : RAMB16_S9
|
||||
generic map (
|
||||
INIT_00 => X"00000000000000000000000000000000ff00000000ff18000600060004008400",
|
||||
INIT_00 => X"00000000000000000000000000000000ff00000000ff18000700070005008500",
|
||||
INIT_01 => X"000000000000000000000000000000000000012000002000d800d800ff700000",
|
||||
INIT_02 => X"0000000000000010000000000000000000010060006060000000000000000000",
|
||||
INIT_03 => X"0000000000201000000000000000000000000000000000000000000000000000",
|
||||
INIT_04 => X"31030030300300220200210200200200000400000400000400000400000420ff",
|
||||
INIT_05 => X"000055550000000300ff000002000000000400000000ff000002000000000031",
|
||||
INIT_06 => X"00000000000080000000000000ff10000020ff00000000200000000000000000",
|
||||
INIT_07 => X"ff0000ff0100000000000010ff009000000000ff00000000001000ff00000000",
|
||||
INIT_08 => X"000000000020ff000100ff000000002000000000000000ff00000000000010ff",
|
||||
INIT_09 => X"000000000000000000200000002028000000000000ff00001000000400100400",
|
||||
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_06 => X"0000000000001000000000110000001811110000100000000000000000000000",
|
||||
INIT_07 => X"0000000020000000100000000000101a1011000000101c101a10110000001000",
|
||||
INIT_08 => X"ff00000000001000ff0000000000000000000080000000000000ff10000020ff",
|
||||
INIT_09 => X"00000000ff00000000000010ffff0000ff0100000000000010ff009000000000",
|
||||
INIT_0A => X"0000ff00001000000500100500000000000020ff000100ff0000000020000000",
|
||||
INIT_0B => X"0000000000000000000000000000000000000000000020000000202800000000",
|
||||
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
|
@ -272,18 +272,18 @@ INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000")
|
|||
|
||||
RAMB16_S9_inst3 : RAMB16_S9
|
||||
generic map (
|
||||
INIT_00 => X"4c4844403c3834302c2824201c181410980e008004fd2a00c800e000dc00d001",
|
||||
INIT_01 => X"504c4844403c3834302c2824201c18141000082410200060125c1058fc005450",
|
||||
INIT_00 => X"4c4844403c3834302c2824201c181410980e008004fd2a009800b000a800a001",
|
||||
INIT_01 => X"504c4844403c3834302c2824201c181410003b2410200060125c1058fc005450",
|
||||
INIT_02 => X"0c08040000083c0048080c440840043c006000000800000801681360115c5854",
|
||||
INIT_03 => X"00080c000810121900082c2824201c1814100c08040000082c2824201c181410",
|
||||
INIT_04 => X"31340030303000221400211200201000141400131300121200111100101000f8",
|
||||
INIT_04 => X"31340030303000221400211200201000111400221300551200661100441000f0",
|
||||
INIT_05 => X"000055550400003802ff00001800ff00001804000002ff00001600ff00000031",
|
||||
INIT_06 => X"000dc800030a210d0000101418e021080000fc020000200000c6040000200400",
|
||||
INIT_07 => X"fc57c8fc0030c800050a0f06fc1c211014181ce020081014182100f6000001c8",
|
||||
INIT_08 => X"180800100000fd001010e801080020001808001049c810e820081014181c06f4",
|
||||
INIT_09 => X"000000000000000000001010200000207084080000fa0400210000dc0000bc00",
|
||||
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_06 => X"0004ff0000042100040004110004042111110404210004ff0000040000200400",
|
||||
INIT_07 => X"020000200000f908121800040008210021000004082100210021000004081218",
|
||||
INIT_08 => X"e020081014182100f6000001fb000dfb00030a210d0000101418e021080000fc",
|
||||
INIT_09 => X"1049fb10e820081014181c06f4fc57fbfc3330fb00050a0f06fc1c211014181c",
|
||||
INIT_0A => X"0000fa0400210000a800008800180800100000fd004310e80108002000180800",
|
||||
INIT_0B => X"0000000000000000000000000000000000000000000000101020000020708408",
|
||||
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
|
|
|
@ -18,9 +18,9 @@ vcom -93 -work work ../uart.vhd
|
|||
vcom -93 -work work ../ram_image.vhd
|
||||
vcom -93 -work work ../plasma_TB.vhd
|
||||
|
||||
vsim -t 1ps tbench
|
||||
view wave
|
||||
#add wave *
|
||||
vsim -t 1ps plasma_tb
|
||||
#view wave
|
||||
add wave *
|
||||
do wave.do
|
||||
|
||||
view structure
|
||||
|
|
|
@ -0,0 +1,51 @@
|
|||
#!/bin/sh
|
||||
# $Id: xilinx_ghdl_simprim 88 2007-10-12 20:37:45Z mueller $
|
||||
#
|
||||
if [ -z "$XILINX" ]
|
||||
then
|
||||
echo "XILINX not defined"
|
||||
exit 1
|
||||
fi
|
||||
#
|
||||
cd $XILINX
|
||||
echo "============================================================"
|
||||
echo "* Build ghdl SIMPRIM libs for $XILINX"
|
||||
echo "============================================================"
|
||||
#
|
||||
if [ ! -d ghdl ]
|
||||
then
|
||||
mkdir ghdl
|
||||
fi
|
||||
#
|
||||
cd $XILINX/ghdl
|
||||
if [ ! -d simprim ]
|
||||
then
|
||||
mkdir simprim
|
||||
fi
|
||||
#
|
||||
cd $XILINX/ghdl/simprim
|
||||
cp $XILINX/vhdl/src/simprims/simprim_Vcomponents.vhd .
|
||||
cp $XILINX/vhdl/src/simprims/simprim_Vpackage.vhd .
|
||||
#
|
||||
if [ ! -d simprim_vital_chop ]
|
||||
then
|
||||
mkdir simprim_vital_chop
|
||||
fi
|
||||
cd simprim_vital_chop
|
||||
xilinx_vhdl_chop $XILINX/vhdl/src/simprims/simprim_VITAL.vhd
|
||||
#
|
||||
cd ..
|
||||
echo "# ghdl ... simprim_Vcomponents.vhd"
|
||||
ghdl -a --ieee=synopsys --work=simprim simprim_Vcomponents.vhd
|
||||
echo "# ghdl ... simprim_Vpackage.vhd"
|
||||
ghdl -a --ieee=synopsys --work=simprim simprim_Vpackage.vhd
|
||||
|
||||
for file in `find simprim_vital_chop -name "*.vhd"`
|
||||
do
|
||||
echo "# ghdl ... $file"
|
||||
ghdl -a -fexplicit --ieee=synopsys --work=simprim 2>&1 $file |\
|
||||
tee $file.ghdl.log
|
||||
done
|
||||
#
|
||||
echo "--- scan for compilation errors:"
|
||||
find
|
|
@ -0,0 +1,52 @@
|
|||
#!/bin/sh
|
||||
# $Id: xilinx_ghdl_unisim 88 2007-10-12 20:37:45Z mueller $
|
||||
#
|
||||
if [ -z "$XILINX" ]
|
||||
then
|
||||
echo "XILINX not defined"
|
||||
exit 1
|
||||
fi
|
||||
#
|
||||
cd $XILINX
|
||||
echo "============================================================"
|
||||
echo "* Build ghdl UNISIM libs for $XILINX"
|
||||
echo "============================================================"
|
||||
#
|
||||
if [ ! -d ghdl ]
|
||||
then
|
||||
mkdir ghdl
|
||||
fi
|
||||
#
|
||||
cd $XILINX/ghdl
|
||||
if [ ! -d unisim ]
|
||||
then
|
||||
mkdir unisim
|
||||
fi
|
||||
#
|
||||
cd $XILINX/ghdl/unisim
|
||||
cp $XILINX/vhdl/src/unisims/unisim_VCOMP.vhd .
|
||||
cp $XILINX/vhdl/src/unisims/unisim_VPKG.vhd .
|
||||
#
|
||||
if [ ! -d unisim_vital_chop ]
|
||||
then
|
||||
mkdir unisim_vital_chop
|
||||
fi
|
||||
cd unisim_vital_chop
|
||||
xilinx_vhdl_chop $XILINX/vhdl/src/unisims/unisim_VITAL.vhd
|
||||
#
|
||||
cd ..
|
||||
echo "# ghdl ... unisim_VCOMP.vhd"
|
||||
ghdl -a --ieee=synopsys --work=unisim unisim_VCOMP.vhd
|
||||
echo "# ghdl ... unisim_VPKG.vhd"
|
||||
ghdl -a --ieee=synopsys --work=unisim unisim_VPKG.vhd
|
||||
|
||||
for file in `find unisim_vital_chop -name "*.vhd"`
|
||||
do
|
||||
echo "# ghdl ... $file"
|
||||
ghdl -a -fexplicit --ieee=synopsys --work=unisim 2>&1 $file |\
|
||||
tee $file.ghdl.log
|
||||
done
|
||||
#
|
||||
echo "--- scan for compilation errors:"
|
||||
find unisim_vital_chop -name "*.ghdl.log" | xargs grep error
|
||||
#
|
|
@ -0,0 +1,38 @@
|
|||
#!/usr/bin/perl -w
|
||||
# $Id: xilinx_vhdl_chop 87 2007-10-06 15:21:26Z mueller $
|
||||
#
|
||||
# Copyright 2007- by Walter F.J. Mueller <W.F.J.Mueller@xxxxxx>
|
||||
#
|
||||
# This program is free software; you may redistribute and/or modify it under
|
||||
# the terms of the GNU General Public License Version 2 as published by the
|
||||
# Free Software Foundation.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful, but
|
||||
# WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
|
||||
# or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
||||
# for complete details.
|
||||
#
|
||||
#
|
||||
# splits a xilinx unisim_VITAL.vhd file along separators looking like:
|
||||
#
|
||||
# -- $Header: <path>/and5b1.vhd,v 1.4 2004/04/08 18:46:23 patrickp Exp $
|
||||
#
|
||||
|
||||
use 5.003; # require Perl 5.003 or higher
|
||||
use strict; # require strict checking
|
||||
|
||||
while (<>) {
|
||||
chomp;
|
||||
my @line = split;
|
||||
if (/^-- \$Header/) {
|
||||
my @file = split(/\//,$line[2]);
|
||||
my $name = $file[$#file];
|
||||
$name =~ s/,v//;
|
||||
print "writing $name \n";
|
||||
close(OFILE);
|
||||
open(OFILE, "> $name") or die "Couldn't open output file: $!\n";
|
||||
}
|
||||
print OFILE $_,"\n";
|
||||
}
|
||||
close(OFILE);
|
||||
|
Loading…
Reference in New Issue