mirror of
git://projects.qi-hardware.com/nn-usb-fpga.git
synced 2024-12-12 20:44:05 +02:00
1000 lines
28 KiB
C
1000 lines
28 KiB
C
/*-------------------------------------------------------------------
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-- TITLE: Plasma CPU in software. Executes MIPS(tm) opcodes.
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-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
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-- DATE CREATED: 1/31/01
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-- FILENAME: mlite.c
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-- PROJECT: Plasma CPU core
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-- COPYRIGHT: Software placed into the public domain by the author.
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-- Software 'as is' without warranty. Author liable for nothing.
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-- DESCRIPTION:
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-- Plasma CPU simulator in C code.
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-- This file served as the starting point for the VHDL code.
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-- Assumes running on a little endian PC.
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--------------------------------------------------------------------*/
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#include <stdio.h>
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#include <stdlib.h>
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#include <string.h>
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#include <ctype.h>
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#include <assert.h>
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//#define ENABLE_CACHE
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#define SIMPLE_CACHE
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#define MEM_SIZE (1024*1024*2)
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#define ntohs(A) ( ((A)>>8) | (((A)&0xff)<<8) )
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#define htons(A) ntohs(A)
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#define ntohl(A) ( ((A)>>24) | (((A)&0xff0000)>>8) | (((A)&0xff00)<<8) | ((A)<<24) )
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#define htonl(A) ntohl(A)
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#ifndef WIN32
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//Support for Linux
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#define putch putchar
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#include <termios.h>
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#include <unistd.h>
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void Sleep(unsigned int value)
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{
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usleep(value * 1000);
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}
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int kbhit(void)
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{
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struct termios oldt, newt;
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struct timeval tv;
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fd_set read_fd;
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tcgetattr(STDIN_FILENO, &oldt);
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newt = oldt;
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newt.c_lflag &= ~(ICANON | ECHO);
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tcsetattr(STDIN_FILENO, TCSANOW, &newt);
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tv.tv_sec=0;
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tv.tv_usec=0;
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FD_ZERO(&read_fd);
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FD_SET(0,&read_fd);
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if(select(1, &read_fd, NULL, NULL, &tv) == -1)
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return 0;
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//tcsetattr(STDIN_FILENO, TCSANOW, &oldt);
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if(FD_ISSET(0,&read_fd))
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return 1;
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return 0;
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}
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int getch(void)
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{
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struct termios oldt, newt;
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int ch;
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tcgetattr(STDIN_FILENO, &oldt);
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newt = oldt;
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newt.c_lflag &= ~(ICANON | ECHO);
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tcsetattr(STDIN_FILENO, TCSANOW, &newt);
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ch = getchar();
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//tcsetattr(STDIN_FILENO, TCSANOW, &oldt);
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return ch;
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}
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#else
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//Support for Windows
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#include <conio.h>
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extern void __stdcall Sleep(unsigned long value);
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#endif
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#define UART_WRITE 0x20000000
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#define UART_READ 0x20000000
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#define IRQ_MASK 0x20000010
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#define IRQ_STATUS 0x20000020
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#define CONFIG_REG 0x20000070
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#define MMU_PROCESS_ID 0x20000080
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#define MMU_FAULT_ADDR 0x20000090
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#define MMU_TLB 0x200000a0
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#define IRQ_UART_READ_AVAILABLE 0x001
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#define IRQ_UART_WRITE_AVAILABLE 0x002
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#define IRQ_COUNTER18_NOT 0x004
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#define IRQ_COUNTER18 0x008
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#define IRQ_MMU 0x200
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#define MMU_ENTRIES 4
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#define MMU_MASK (1024*4-1)
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typedef struct
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{
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unsigned int virtualAddress;
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unsigned int physicalAddress;
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} MmuEntry;
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typedef struct {
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int r[32];
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int pc, pc_next, epc;
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unsigned int hi;
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unsigned int lo;
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int status;
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int userMode;
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int processId;
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int exceptionId;
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int faultAddr;
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int irqStatus;
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int skip;
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unsigned char *mem;
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int wakeup;
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int big_endian;
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MmuEntry mmuEntry[MMU_ENTRIES];
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} State;
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static char *opcode_string[]={
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"SPECIAL","REGIMM","J","JAL","BEQ","BNE","BLEZ","BGTZ",
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"ADDI","ADDIU","SLTI","SLTIU","ANDI","ORI","XORI","LUI",
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"COP0","COP1","COP2","COP3","BEQL","BNEL","BLEZL","BGTZL",
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"?","?","?","?","?","?","?","?",
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"LB","LH","LWL","LW","LBU","LHU","LWR","?",
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"SB","SH","SWL","SW","?","?","SWR","CACHE",
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"LL","LWC1","LWC2","LWC3","?","LDC1","LDC2","LDC3"
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"SC","SWC1","SWC2","SWC3","?","SDC1","SDC2","SDC3"
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};
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static char *special_string[]={
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"SLL","?","SRL","SRA","SLLV","?","SRLV","SRAV",
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"JR","JALR","MOVZ","MOVN","SYSCALL","BREAK","?","SYNC",
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"MFHI","MTHI","MFLO","MTLO","?","?","?","?",
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"MULT","MULTU","DIV","DIVU","?","?","?","?",
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"ADD","ADDU","SUB","SUBU","AND","OR","XOR","NOR",
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"?","?","SLT","SLTU","?","DADDU","?","?",
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"TGE","TGEU","TLT","TLTU","TEQ","?","TNE","?",
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"?","?","?","?","?","?","?","?"
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};
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static char *regimm_string[]={
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"BLTZ","BGEZ","BLTZL","BGEZL","?","?","?","?",
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"TGEI","TGEIU","TLTI","TLTIU","TEQI","?","TNEI","?",
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"BLTZAL","BEQZAL","BLTZALL","BGEZALL","?","?","?","?",
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"?","?","?","?","?","?","?","?"
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};
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static unsigned int HWMemory[8];
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static int mem_read(State *s, int size, unsigned int address)
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{
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unsigned int value=0, ptr;
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s->irqStatus |= IRQ_UART_WRITE_AVAILABLE;
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switch(address)
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{
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case UART_READ:
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if(kbhit())
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HWMemory[0] = getch();
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s->irqStatus &= ~IRQ_UART_READ_AVAILABLE; //clear bit
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return HWMemory[0];
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case IRQ_MASK:
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return HWMemory[1];
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case IRQ_MASK + 4:
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Sleep(10);
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return 0;
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case IRQ_STATUS:
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if(kbhit())
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s->irqStatus |= IRQ_UART_READ_AVAILABLE;
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return s->irqStatus;
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case MMU_PROCESS_ID:
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return s->processId;
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case MMU_FAULT_ADDR:
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return s->faultAddr;
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}
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ptr = (unsigned int)s->mem + (address % MEM_SIZE);
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if(0x10000000 <= address && address < 0x10000000 + 1024*1024)
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ptr += 1024*1024;
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switch(size)
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{
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case 4:
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if(address & 3)
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printf("Unaligned access PC=0x%x address=0x%x\n", (int)s->pc, (int)address);
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assert((address & 3) == 0);
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value = *(int*)ptr;
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if(s->big_endian)
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value = ntohl(value);
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break;
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case 2:
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assert((address & 1) == 0);
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value = *(unsigned short*)ptr;
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if(s->big_endian)
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value = ntohs((unsigned short)value);
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break;
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case 1:
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value = *(unsigned char*)ptr;
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break;
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default:
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printf("ERROR");
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}
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return(value);
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}
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static void mem_write(State *s, int size, int unsigned address, unsigned int value)
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{
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unsigned int ptr;
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switch(address)
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{
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case UART_WRITE:
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putch(value);
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fflush(stdout);
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return;
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case IRQ_MASK:
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HWMemory[1] = value;
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return;
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case IRQ_STATUS:
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s->irqStatus = value;
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return;
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case CONFIG_REG:
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return;
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case MMU_PROCESS_ID:
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//printf("processId=%d\n", value);
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s->processId = value;
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return;
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}
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if(MMU_TLB <= address && address <= MMU_TLB+MMU_ENTRIES * 8)
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{
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//printf("TLB 0x%x 0x%x\n", address - MMU_TLB, value);
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ptr = (unsigned int)s->mmuEntry + address - MMU_TLB;
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*(int*)ptr = value;
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s->irqStatus &= ~IRQ_MMU;
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return;
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}
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ptr = (unsigned int)s->mem + (address % MEM_SIZE);
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if(0x10000000 <= address && address < 0x10000000 + 1024*1024)
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ptr += 1024*1024;
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switch(size)
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{
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case 4:
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assert((address & 3) == 0);
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if(s->big_endian)
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value = htonl(value);
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*(int*)ptr = value;
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break;
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case 2:
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assert((address & 1) == 0);
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if(s->big_endian)
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value = htons((unsigned short)value);
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*(short*)ptr = (unsigned short)value;
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break;
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case 1:
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*(char*)ptr = (unsigned char)value;
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break;
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default:
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printf("ERROR");
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}
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}
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#ifdef ENABLE_CACHE
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/************* Optional MMU and cache implementation *************/
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/* TAG = VirtualAddress | ProcessId | WriteableBit */
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unsigned int mmu_lookup(State *s, unsigned int processId,
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unsigned int address, int write)
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{
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int i;
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unsigned int compare, tag;
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if(processId == 0 || s->userMode == 0)
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return address;
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//if(address < 0x30000000)
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// return address;
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compare = (address & ~MMU_MASK) | (processId << 1);
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for(i = 0; i < MMU_ENTRIES; ++i)
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{
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tag = s->mmuEntry[i].virtualAddress;
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if((tag & ~1) == compare && (write == 0 || (tag & 1)))
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return s->mmuEntry[i].physicalAddress | (address & MMU_MASK);
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}
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//printf("\nMMUTlbMiss 0x%x PC=0x%x w=%d pid=%d user=%d\n",
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// address, s->pc, write, processId, s->userMode);
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//printf("m");
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s->exceptionId = 1;
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s->faultAddr = address & ~MMU_MASK;
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s->irqStatus |= IRQ_MMU;
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return address;
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}
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#define CACHE_SET_ASSOC_LN2 0
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#define CACHE_SET_ASSOC (1 << CACHE_SET_ASSOC_LN2)
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#define CACHE_SIZE_LN2 (13 - CACHE_SET_ASSOC_LN2) //8 KB
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#define CACHE_SIZE (1 << CACHE_SIZE_LN2)
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#define CACHE_LINE_SIZE_LN2 2 //4 bytes
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#define CACHE_LINE_SIZE (1 << CACHE_LINE_SIZE_LN2)
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static int cacheData[CACHE_SET_ASSOC][CACHE_SIZE/sizeof(int)];
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static int cacheAddr[CACHE_SET_ASSOC][CACHE_SIZE/CACHE_LINE_SIZE];
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static int cacheSetNext;
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static int cacheMiss, cacheWriteBack, cacheCount;
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static void cache_init(void)
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{
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int set, i;
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for(set = 0; set < CACHE_SET_ASSOC; ++set)
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{
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for(i = 0; i < CACHE_SIZE/CACHE_LINE_SIZE; ++i)
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cacheAddr[set][i] = 0xffff0000;
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}
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}
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/* Write-back cache memory tagged by virtual address and processId */
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/* TAG = virtualAddress | processId | dirtyBit */
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static int cache_load(State *s, unsigned int address, int write)
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{
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int set, i, pid, miss, offsetAddr, offsetData, offsetMem;
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unsigned int addrTagMatch, addrPrevMatch=0;
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unsigned int addrPrev;
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unsigned int addressPhysical, tag;
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++cacheCount;
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addrTagMatch = address & ~(CACHE_SIZE-1);
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offsetAddr = (address & (CACHE_SIZE-1)) >> CACHE_LINE_SIZE_LN2;
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/* Find match */
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miss = 1;
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for(set = 0; set < CACHE_SET_ASSOC; ++set)
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{
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addrPrevMatch = cacheAddr[set][offsetAddr] & ~(CACHE_SIZE-1);
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if(addrPrevMatch == addrTagMatch)
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{
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miss = 0;
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break;
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}
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}
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/* Cache miss? */
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if(miss)
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{
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++cacheMiss;
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set = cacheSetNext;
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cacheSetNext = (cacheSetNext + 1) & (CACHE_SET_ASSOC-1);
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}
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//else if(write || (address >> 28) != 0x1)
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//{
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// tag = cacheAddr[set][offsetAddr];
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// pid = (tag & (CACHE_SIZE-1)) >> 1;
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// if(pid != s->processId)
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// miss = 1;
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//}
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if(miss)
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{
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offsetData = address & (CACHE_SIZE-1) & ~(CACHE_LINE_SIZE-1);
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/* Cache line dirty? */
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if(cacheAddr[set][offsetAddr] & 1)
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{
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/* Write back cache line */
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tag = cacheAddr[set][offsetAddr];
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addrPrev = tag & ~(CACHE_SIZE-1);
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addrPrev |= address & (CACHE_SIZE-1);
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pid = (tag & (CACHE_SIZE-1)) >> 1;
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addressPhysical = mmu_lookup(s, pid, addrPrev, 1); //virtual->physical
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if(s->exceptionId)
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return 0;
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offsetMem = addressPhysical & ~(CACHE_LINE_SIZE-1);
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for(i = 0; i < CACHE_LINE_SIZE; i += 4)
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mem_write(s, 4, offsetMem + i, cacheData[set][(offsetData + i) >> 2]);
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++cacheWriteBack;
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}
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/* Read cache line */
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addressPhysical = mmu_lookup(s, s->processId, address, write); //virtual->physical
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if(s->exceptionId)
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return 0;
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offsetMem = addressPhysical & ~(CACHE_LINE_SIZE-1);
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cacheAddr[set][offsetAddr] = addrTagMatch;
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for(i = 0; i < CACHE_LINE_SIZE; i += 4)
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cacheData[set][(offsetData + i) >> 2] = mem_read(s, 4, offsetMem + i);
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}
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cacheAddr[set][offsetAddr] |= write;
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return set;
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}
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static int cache_read(State *s, int size, unsigned int address)
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{
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int set, offset;
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int value;
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if((address & 0xfe000000) != 0x10000000)
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return mem_read(s, size, address);
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set = cache_load(s, address, 0);
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if(s->exceptionId)
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return 0;
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offset = (address & (CACHE_SIZE-1)) >> 2;
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value = cacheData[set][offset];
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if(s->big_endian)
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address ^= 3;
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switch(size)
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{
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case 2:
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value = (value >> ((address & 2) << 3)) & 0xffff;
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break;
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case 1:
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value = (value >> ((address & 3) << 3)) & 0xff;
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break;
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}
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return value;
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}
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static void cache_write(State *s, int size, int unsigned address, unsigned int value)
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{
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int set, offset;
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unsigned int mask;
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if((address >> 28) != 0x1) // && (s->processId == 0 || s->userMode == 0))
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{
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mem_write(s, size, address, value);
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return;
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}
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set = cache_load(s, address, 1);
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if(s->exceptionId)
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return;
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offset = (address & (CACHE_SIZE-1)) >> 2;
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if(s->big_endian)
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address ^= 3;
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switch(size)
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{
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case 2:
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value &= 0xffff;
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value |= value << 16;
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mask = 0xffff << ((address & 2) << 3);
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break;
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case 1:
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value &= 0xff;
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value |= (value << 8) | (value << 16) | (value << 24);
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mask = 0xff << ((address & 3) << 3);
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break;
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case 4:
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default:
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mask = 0xffffffff;
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break;
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}
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cacheData[set][offset] = (value & mask) | (cacheData[set][offset] & ~mask);
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}
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#define mem_read cache_read
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#define mem_write cache_write
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#else
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static void cache_init(void) {}
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#endif
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#ifdef SIMPLE_CACHE
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//Write through direct mapped 4KB cache
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#define CACHE_MISS 0x1ff
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static unsigned int cacheData[1024];
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static unsigned int cacheAddr[1024]; //9-bit addresses
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static int cacheTry, cacheMiss, cacheInit;
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static int cache_read(State *s, int size, unsigned int address)
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{
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int offset;
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unsigned int value, value2, address2=address;
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if(cacheInit == 0)
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{
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cacheInit = 1;
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for(offset = 0; offset < 1024; ++offset)
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cacheAddr[offset] = CACHE_MISS;
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}
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offset = address >> 20;
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if(offset != 0x100 && offset != 0x101)
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return mem_read(s, size, address);
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++cacheTry;
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offset = (address >> 2) & 0x3ff;
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if(cacheAddr[offset] != (address >> 12) || cacheAddr[offset] == CACHE_MISS)
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{
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++cacheMiss;
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cacheAddr[offset] = address >> 12;
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cacheData[offset] = mem_read(s, 4, address & ~3);
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}
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value = cacheData[offset];
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if(s->big_endian)
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address ^= 3;
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switch(size)
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{
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case 2:
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value = (value >> ((address & 2) << 3)) & 0xffff;
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break;
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case 1:
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value = (value >> ((address & 3) << 3)) & 0xff;
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break;
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}
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//Debug testing
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value2 = mem_read(s, size, address2);
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if(value != value2)
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printf("miss match\n");
|
|
//if((cacheTry & 0xffff) == 0) printf("\n***cache(%d,%d)\n ", cacheMiss, cacheTry);
|
|
return value;
|
|
}
|
|
|
|
static void cache_write(State *s, int size, int unsigned address, unsigned int value)
|
|
{
|
|
int offset;
|
|
|
|
mem_write(s, size, address, value);
|
|
|
|
offset = address >> 20;
|
|
if(offset != 0x100 && offset != 0x101)
|
|
return;
|
|
|
|
offset = (address >> 2) & 0x3ff;
|
|
if(size != 4)
|
|
{
|
|
cacheAddr[offset] = CACHE_MISS;
|
|
return;
|
|
}
|
|
cacheAddr[offset] = address >> 12;
|
|
cacheData[offset] = value;
|
|
}
|
|
|
|
#define mem_read cache_read
|
|
#define mem_write cache_write
|
|
#endif //SIMPLE_CACHE
|
|
/************* End optional cache implementation *************/
|
|
|
|
|
|
void mult_big(unsigned int a,
|
|
unsigned int b,
|
|
unsigned int *hi,
|
|
unsigned int *lo)
|
|
{
|
|
unsigned int ahi, alo, bhi, blo;
|
|
unsigned int c0, c1, c2;
|
|
unsigned int c1_a, c1_b;
|
|
|
|
ahi = a >> 16;
|
|
alo = a & 0xffff;
|
|
bhi = b >> 16;
|
|
blo = b & 0xffff;
|
|
|
|
c0 = alo * blo;
|
|
c1_a = ahi * blo;
|
|
c1_b = alo * bhi;
|
|
c2 = ahi * bhi;
|
|
|
|
c2 += (c1_a >> 16) + (c1_b >> 16);
|
|
c1 = (c1_a & 0xffff) + (c1_b & 0xffff) + (c0 >> 16);
|
|
c2 += (c1 >> 16);
|
|
c0 = (c1 << 16) + (c0 & 0xffff);
|
|
*hi = c2;
|
|
*lo = c0;
|
|
}
|
|
|
|
void mult_big_signed(int a,
|
|
int b,
|
|
unsigned int *hi,
|
|
unsigned int *lo)
|
|
{
|
|
unsigned int ahi, alo, bhi, blo;
|
|
unsigned int c0, c1, c2;
|
|
unsigned int c1_a, c1_b;
|
|
|
|
ahi = a >> 16;
|
|
alo = a & 0xffff;
|
|
bhi = b >> 16;
|
|
blo = b & 0xffff;
|
|
|
|
c0 = alo * blo;
|
|
c1_a = ahi * blo;
|
|
c1_b = alo * bhi;
|
|
c2 = ahi * bhi;
|
|
|
|
c2 += (c1_a >> 16) + (c1_b >> 16);
|
|
c1 = (c1_a & 0xffff) + (c1_b & 0xffff) + (c0 >> 16);
|
|
c2 += (c1 >> 16);
|
|
c0 = (c1 << 16) + (c0 & 0xffff);
|
|
*hi = c2;
|
|
*lo = c0;
|
|
}
|
|
|
|
//execute one cycle of a Plasma CPU
|
|
void cycle(State *s, int show_mode)
|
|
{
|
|
unsigned int opcode;
|
|
unsigned int op, rs, rt, rd, re, func, imm, target;
|
|
int imm_shift, branch=0, lbranch=2, skip2=0;
|
|
int *r=s->r;
|
|
unsigned int *u=(unsigned int*)s->r;
|
|
unsigned int ptr, epc, rSave;
|
|
|
|
opcode = mem_read(s, 4, s->pc);
|
|
op = (opcode >> 26) & 0x3f;
|
|
rs = (opcode >> 21) & 0x1f;
|
|
rt = (opcode >> 16) & 0x1f;
|
|
rd = (opcode >> 11) & 0x1f;
|
|
re = (opcode >> 6) & 0x1f;
|
|
func = opcode & 0x3f;
|
|
imm = opcode & 0xffff;
|
|
imm_shift = (((int)(short)imm) << 2) - 4;
|
|
target = (opcode << 6) >> 4;
|
|
ptr = (short)imm + r[rs];
|
|
r[0] = 0;
|
|
if(show_mode)
|
|
{
|
|
printf("%8.8x %8.8x ", s->pc, opcode);
|
|
if(op == 0)
|
|
printf("%8s ", special_string[func]);
|
|
else if(op == 1)
|
|
printf("%8s ", regimm_string[rt]);
|
|
else
|
|
printf("%8s ", opcode_string[op]);
|
|
printf("$%2.2d $%2.2d $%2.2d $%2.2d ", rs, rt, rd, re);
|
|
printf("%4.4x", imm);
|
|
if(show_mode == 1)
|
|
printf(" r[%2.2d]=%8.8x r[%2.2d]=%8.8x", rs, r[rs], rt, r[rt]);
|
|
printf("\n");
|
|
}
|
|
if(show_mode > 5)
|
|
return;
|
|
epc = s->pc + 4;
|
|
if(s->pc_next != s->pc + 4)
|
|
epc |= 2; //branch delay slot
|
|
s->pc = s->pc_next;
|
|
s->pc_next = s->pc_next + 4;
|
|
if(s->skip)
|
|
{
|
|
s->skip = 0;
|
|
return;
|
|
}
|
|
rSave = r[rt];
|
|
switch(op)
|
|
{
|
|
case 0x00:/*SPECIAL*/
|
|
switch(func)
|
|
{
|
|
case 0x00:/*SLL*/ r[rd]=r[rt]<<re; break;
|
|
case 0x02:/*SRL*/ r[rd]=u[rt]>>re; break;
|
|
case 0x03:/*SRA*/ r[rd]=r[rt]>>re; break;
|
|
case 0x04:/*SLLV*/ r[rd]=r[rt]<<r[rs]; break;
|
|
case 0x06:/*SRLV*/ r[rd]=u[rt]>>r[rs]; break;
|
|
case 0x07:/*SRAV*/ r[rd]=r[rt]>>r[rs]; break;
|
|
case 0x08:/*JR*/ s->pc_next=r[rs]; break;
|
|
case 0x09:/*JALR*/ r[rd]=s->pc_next; s->pc_next=r[rs]; break;
|
|
case 0x0a:/*MOVZ*/ if(!r[rt]) r[rd]=r[rs]; break; /*IV*/
|
|
case 0x0b:/*MOVN*/ if(r[rt]) r[rd]=r[rs]; break; /*IV*/
|
|
case 0x0c:/*SYSCALL*/ epc|=1; s->exceptionId=1; break;
|
|
case 0x0d:/*BREAK*/ epc|=1; s->exceptionId=1; break;
|
|
case 0x0f:/*SYNC*/ s->wakeup=1; break;
|
|
case 0x10:/*MFHI*/ r[rd]=s->hi; break;
|
|
case 0x11:/*FTHI*/ s->hi=r[rs]; break;
|
|
case 0x12:/*MFLO*/ r[rd]=s->lo; break;
|
|
case 0x13:/*MTLO*/ s->lo=r[rs]; break;
|
|
case 0x18:/*MULT*/ mult_big_signed(r[rs],r[rt],&s->hi,&s->lo); break;
|
|
case 0x19:/*MULTU*/ mult_big(r[rs],r[rt],&s->hi,&s->lo); break;
|
|
case 0x1a:/*DIV*/ s->lo=r[rs]/r[rt]; s->hi=r[rs]%r[rt]; break;
|
|
case 0x1b:/*DIVU*/ s->lo=u[rs]/u[rt]; s->hi=u[rs]%u[rt]; break;
|
|
case 0x20:/*ADD*/ r[rd]=r[rs]+r[rt]; break;
|
|
case 0x21:/*ADDU*/ r[rd]=r[rs]+r[rt]; break;
|
|
case 0x22:/*SUB*/ r[rd]=r[rs]-r[rt]; break;
|
|
case 0x23:/*SUBU*/ r[rd]=r[rs]-r[rt]; break;
|
|
case 0x24:/*AND*/ r[rd]=r[rs]&r[rt]; break;
|
|
case 0x25:/*OR*/ r[rd]=r[rs]|r[rt]; break;
|
|
case 0x26:/*XOR*/ r[rd]=r[rs]^r[rt]; break;
|
|
case 0x27:/*NOR*/ r[rd]=~(r[rs]|r[rt]); break;
|
|
case 0x2a:/*SLT*/ r[rd]=r[rs]<r[rt]; break;
|
|
case 0x2b:/*SLTU*/ r[rd]=u[rs]<u[rt]; break;
|
|
case 0x2d:/*DADDU*/r[rd]=r[rs]+u[rt]; break;
|
|
case 0x31:/*TGEU*/ break;
|
|
case 0x32:/*TLT*/ break;
|
|
case 0x33:/*TLTU*/ break;
|
|
case 0x34:/*TEQ*/ break;
|
|
case 0x36:/*TNE*/ break;
|
|
default: printf("ERROR0(*0x%x~0x%x)\n", s->pc, opcode);
|
|
s->wakeup=1;
|
|
}
|
|
break;
|
|
case 0x01:/*REGIMM*/
|
|
switch(rt) {
|
|
case 0x10:/*BLTZAL*/ r[31]=s->pc_next;
|
|
case 0x00:/*BLTZ*/ branch=r[rs]<0; break;
|
|
case 0x11:/*BGEZAL*/ r[31]=s->pc_next;
|
|
case 0x01:/*BGEZ*/ branch=r[rs]>=0; break;
|
|
case 0x12:/*BLTZALL*/r[31]=s->pc_next;
|
|
case 0x02:/*BLTZL*/ lbranch=r[rs]<0; break;
|
|
case 0x13:/*BGEZALL*/r[31]=s->pc_next;
|
|
case 0x03:/*BGEZL*/ lbranch=r[rs]>=0; break;
|
|
default: printf("ERROR1\n"); s->wakeup=1;
|
|
}
|
|
break;
|
|
case 0x03:/*JAL*/ r[31]=s->pc_next;
|
|
case 0x02:/*J*/ s->pc_next=(s->pc&0xf0000000)|target; break;
|
|
case 0x04:/*BEQ*/ branch=r[rs]==r[rt]; break;
|
|
case 0x05:/*BNE*/ branch=r[rs]!=r[rt]; break;
|
|
case 0x06:/*BLEZ*/ branch=r[rs]<=0; break;
|
|
case 0x07:/*BGTZ*/ branch=r[rs]>0; break;
|
|
case 0x08:/*ADDI*/ r[rt]=r[rs]+(short)imm; break;
|
|
case 0x09:/*ADDIU*/ u[rt]=u[rs]+(short)imm; break;
|
|
case 0x0a:/*SLTI*/ r[rt]=r[rs]<(short)imm; break;
|
|
case 0x0b:/*SLTIU*/ u[rt]=u[rs]<(unsigned int)(short)imm; break;
|
|
case 0x0c:/*ANDI*/ r[rt]=r[rs]&imm; break;
|
|
case 0x0d:/*ORI*/ r[rt]=r[rs]|imm; break;
|
|
case 0x0e:/*XORI*/ r[rt]=r[rs]^imm; break;
|
|
case 0x0f:/*LUI*/ r[rt]=(imm<<16); break;
|
|
case 0x10:/*COP0*/
|
|
if((opcode & (1<<23)) == 0) //move from CP0
|
|
{
|
|
if(rd == 12)
|
|
r[rt]=s->status;
|
|
else
|
|
r[rt]=s->epc;
|
|
}
|
|
else //move to CP0
|
|
{
|
|
s->status=r[rt]&1;
|
|
if(s->processId && (r[rt]&2))
|
|
{
|
|
s->userMode|=r[rt]&2;
|
|
//printf("CpuStatus=%d %d %d\n", r[rt], s->status, s->userMode);
|
|
//s->wakeup = 1;
|
|
//printf("pc=0x%x\n", epc);
|
|
}
|
|
}
|
|
break;
|
|
// case 0x11:/*COP1*/ break;
|
|
// case 0x12:/*COP2*/ break;
|
|
// case 0x13:/*COP3*/ break;
|
|
case 0x14:/*BEQL*/ lbranch=r[rs]==r[rt]; break;
|
|
case 0x15:/*BNEL*/ lbranch=r[rs]!=r[rt]; break;
|
|
case 0x16:/*BLEZL*/ lbranch=r[rs]<=0; break;
|
|
case 0x17:/*BGTZL*/ lbranch=r[rs]>0; break;
|
|
// case 0x1c:/*MAD*/ break; /*IV*/
|
|
case 0x20:/*LB*/ r[rt]=(signed char)mem_read(s,1,ptr); break;
|
|
case 0x21:/*LH*/ r[rt]=(signed short)mem_read(s,2,ptr); break;
|
|
case 0x22:/*LWL*/
|
|
//target=8*(ptr&3);
|
|
//r[rt]=(r[rt]&~(0xffffffff<<target))|
|
|
// (mem_read(s,4,ptr&~3)<<target); break;
|
|
case 0x23:/*LW*/ r[rt]=mem_read(s,4,ptr); break;
|
|
case 0x24:/*LBU*/ r[rt]=(unsigned char)mem_read(s,1,ptr); break;
|
|
case 0x25:/*LHU*/ r[rt]=(unsigned short)mem_read(s,2,ptr); break;
|
|
case 0x26:/*LWR*/
|
|
//target=32-8*(ptr&3);
|
|
//r[rt]=(r[rt]&~((unsigned int)0xffffffff>>target))|
|
|
//((unsigned int)mem_read(s,4,ptr&~3)>>target);
|
|
break;
|
|
case 0x28:/*SB*/ mem_write(s,1,ptr,r[rt]); break;
|
|
case 0x29:/*SH*/ mem_write(s,2,ptr,r[rt]); break;
|
|
case 0x2a:/*SWL*/
|
|
//mem_write(s,1,ptr,r[rt]>>24);
|
|
//mem_write(s,1,ptr+1,r[rt]>>16);
|
|
//mem_write(s,1,ptr+2,r[rt]>>8);
|
|
//mem_write(s,1,ptr+3,r[rt]); break;
|
|
case 0x2b:/*SW*/ mem_write(s,4,ptr,r[rt]); break;
|
|
case 0x2e:/*SWR*/ break; //fixme
|
|
case 0x2f:/*CACHE*/break;
|
|
case 0x30:/*LL*/ r[rt]=mem_read(s,4,ptr); break;
|
|
// case 0x31:/*LWC1*/ break;
|
|
// case 0x32:/*LWC2*/ break;
|
|
// case 0x33:/*LWC3*/ break;
|
|
// case 0x35:/*LDC1*/ break;
|
|
// case 0x36:/*LDC2*/ break;
|
|
// case 0x37:/*LDC3*/ break;
|
|
// case 0x38:/*SC*/ *(int*)ptr=r[rt]; r[rt]=1; break;
|
|
case 0x38:/*SC*/ mem_write(s,4,ptr,r[rt]); r[rt]=1; break;
|
|
// case 0x39:/*SWC1*/ break;
|
|
// case 0x3a:/*SWC2*/ break;
|
|
// case 0x3b:/*SWC3*/ break;
|
|
// case 0x3d:/*SDC1*/ break;
|
|
// case 0x3e:/*SDC2*/ break;
|
|
// case 0x3f:/*SDC3*/ break;
|
|
default: printf("ERROR2 address=0x%x opcode=0x%x\n", s->pc, opcode);
|
|
s->wakeup=1;
|
|
}
|
|
s->pc_next += (branch || lbranch == 1) ? imm_shift : 0;
|
|
s->pc_next &= ~3;
|
|
s->skip = (lbranch == 0) | skip2;
|
|
|
|
if(s->exceptionId)
|
|
{
|
|
r[rt] = rSave;
|
|
s->epc = epc;
|
|
s->pc_next = 0x3c;
|
|
s->skip = 1;
|
|
s->exceptionId = 0;
|
|
s->userMode = 0;
|
|
//s->wakeup = 1;
|
|
return;
|
|
}
|
|
}
|
|
|
|
void show_state(State *s)
|
|
{
|
|
int i,j;
|
|
printf("pid=%d userMode=%d, epc=0x%x\n", s->processId, s->userMode, s->epc);
|
|
for(i = 0; i < 4; ++i)
|
|
{
|
|
printf("%2.2d ", i * 8);
|
|
for(j = 0; j < 8; ++j)
|
|
{
|
|
printf("%8.8x ", s->r[i*8+j]);
|
|
}
|
|
printf("\n");
|
|
}
|
|
//printf("%8.8lx %8.8lx %8.8lx %8.8lx\n", s->pc, s->pc_next, s->hi, s->lo);
|
|
j = s->pc;
|
|
for(i = -4; i <= 8; ++i)
|
|
{
|
|
printf("%c", i==0 ? '*' : ' ');
|
|
s->pc = j + i * 4;
|
|
cycle(s, 10);
|
|
}
|
|
s->pc = j;
|
|
}
|
|
|
|
void do_debug(State *s)
|
|
{
|
|
int ch;
|
|
int i, j=0, watch=0, addr;
|
|
s->pc_next = s->pc + 4;
|
|
s->skip = 0;
|
|
s->wakeup = 0;
|
|
show_state(s);
|
|
ch = ' ';
|
|
for(;;)
|
|
{
|
|
if(ch != 'n')
|
|
{
|
|
if(watch)
|
|
printf("0x%8.8x=0x%8.8x\n", watch, mem_read(s, 4, watch));
|
|
printf("1=Debug 2=Trace 3=Step 4=BreakPt 5=Go 6=Memory ");
|
|
printf("7=Watch 8=Jump 9=Quit> ");
|
|
}
|
|
ch = getch();
|
|
if(ch != 'n')
|
|
printf("\n");
|
|
switch(ch)
|
|
{
|
|
case '1': case 'd': case ' ':
|
|
cycle(s, 0); show_state(s); break;
|
|
case 'n':
|
|
cycle(s, 1); break;
|
|
case '2': case 't':
|
|
cycle(s, 0); printf("*"); cycle(s, 10); break;
|
|
case '3': case 's':
|
|
printf("Count> ");
|
|
scanf("%d", &j);
|
|
for(i = 0; i < j; ++i)
|
|
cycle(s, 1);
|
|
show_state(s);
|
|
break;
|
|
case '4': case 'b':
|
|
printf("Line> ");
|
|
scanf("%x", &j);
|
|
printf("break point=0x%x\n", j);
|
|
break;
|
|
case '5': case 'g':
|
|
s->wakeup = 0;
|
|
cycle(s, 0);
|
|
while(s->wakeup == 0)
|
|
{
|
|
if(s->pc == j)
|
|
break;
|
|
cycle(s, 0);
|
|
}
|
|
show_state(s);
|
|
break;
|
|
case 'G':
|
|
s->wakeup = 0;
|
|
cycle(s, 1);
|
|
while(s->wakeup == 0)
|
|
{
|
|
if(s->pc == j)
|
|
break;
|
|
cycle(s, 1);
|
|
}
|
|
show_state(s);
|
|
break;
|
|
case '6': case 'm':
|
|
printf("Memory> ");
|
|
scanf("%x", &j);
|
|
for(i = 0; i < 8; ++i)
|
|
{
|
|
printf("%8.8x ", mem_read(s, 4, j+i*4));
|
|
}
|
|
printf("\n");
|
|
break;
|
|
case '7': case 'w':
|
|
printf("Watch> ");
|
|
scanf("%x", &watch);
|
|
break;
|
|
case '8': case 'j':
|
|
printf("Jump> ");
|
|
scanf("%x", &addr);
|
|
s->pc = addr;
|
|
s->pc_next = addr + 4;
|
|
show_state(s);
|
|
break;
|
|
case '9': case 'q':
|
|
return;
|
|
}
|
|
}
|
|
}
|
|
/************************************************************/
|
|
|
|
int main(int argc,char *argv[])
|
|
{
|
|
State state, *s=&state;
|
|
FILE *in;
|
|
int bytes, index;
|
|
printf("Plasma emulator\n");
|
|
memset(s, 0, sizeof(State));
|
|
s->big_endian = 1;
|
|
s->mem = (unsigned char*)malloc(MEM_SIZE);
|
|
memset(s->mem, 0, MEM_SIZE);
|
|
if(argc <= 1)
|
|
{
|
|
printf(" Usage: mlite file.exe\n");
|
|
printf(" mlite file.exe B {for big_endian}\n");
|
|
printf(" mlite file.exe L {for little_endian}\n");
|
|
printf(" mlite file.exe BD {disassemble big_endian}\n");
|
|
printf(" mlite file.exe LD {disassemble little_endian}\n");
|
|
|
|
return 0;
|
|
}
|
|
in = fopen(argv[1], "rb");
|
|
if(in == NULL)
|
|
{
|
|
printf("Can't open file %s!\n",argv[1]);
|
|
getch();
|
|
return(0);
|
|
}
|
|
bytes = fread(s->mem, 1, MEM_SIZE, in);
|
|
fclose(in);
|
|
memcpy(s->mem + 1024*1024, s->mem, 1024*1024); //internal 8KB SRAM
|
|
printf("Read %d bytes.\n", bytes);
|
|
cache_init();
|
|
if(argc == 3 && argv[2][0] == 'B')
|
|
{
|
|
printf("Big Endian\n");
|
|
s->big_endian = 1;
|
|
}
|
|
if(argc == 3 && argv[2][0] == 'L')
|
|
{
|
|
printf("Big Endian\n");
|
|
s->big_endian = 0;
|
|
}
|
|
s->processId = 0;
|
|
if(argc == 3 && argv[2][0] == 'S')
|
|
{ /*make big endian*/
|
|
printf("Big Endian\n");
|
|
for(index = 0; index < bytes+3; index += 4)
|
|
{
|
|
*(unsigned int*)&s->mem[index] = htonl(*(unsigned int*)&s->mem[index]);
|
|
}
|
|
in = fopen("big.exe", "wb");
|
|
fwrite(s->mem, bytes, 1, in);
|
|
fclose(in);
|
|
return(0);
|
|
}
|
|
if(argc == 3 && argv[2][1] == 'D')
|
|
{ /*dump image*/
|
|
for(index = 0; index < bytes; index += 4) {
|
|
s->pc = index;
|
|
cycle(s, 10);
|
|
}
|
|
free(s->mem);
|
|
return(0);
|
|
}
|
|
s->pc = 0x0;
|
|
index = mem_read(s, 4, 0);
|
|
if((index & 0xffffff00) == 0x3c1c1000)
|
|
s->pc = 0x10000000;
|
|
do_debug(s);
|
|
free(s->mem);
|
|
return(0);
|
|
}
|
|
|