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284 lines
16 KiB
Plaintext
284 lines
16 KiB
Plaintext
# // ModelSim SE 6.0d Apr 25 2005 Linux 2.6.32-21-generic
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# //
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# // Copyright Mentor Graphics Corporation 2005
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# // All Rights Reserved.
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# //
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# // THIS WORK CONTAINS TRADE SECRET AND
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# // PROPRIETARY INFORMATION WHICH IS THE PROPERTY
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# // OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS
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# // AND IS SUBJECT TO LICENSE TERMS.
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# //
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# do plasma_3e_TB.do
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# Reading /home/opt/cad/modeltech/linux/../modelsim.ini
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# "work" maps to directory work. (Default mapping)
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# Model Technology ModelSim SE vcom 6.0d Compiler 2005.04 Apr 25 2005
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# -- Loading package standard
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# -- Loading package std_logic_1164
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# -- Compiling package mlite_pack
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# -- Compiling package body mlite_pack
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# -- Loading package mlite_pack
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# Model Technology ModelSim SE vcom 6.0d Compiler 2005.04 Apr 25 2005
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# -- Loading package standard
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# -- Loading package std_logic_1164
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# -- Loading package mlite_pack
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# -- Compiling entity plasma
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# -- Compiling architecture logic of plasma
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# Model Technology ModelSim SE vcom 6.0d Compiler 2005.04 Apr 25 2005
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# -- Loading package standard
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# -- Loading package std_logic_1164
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# -- Loading package mlite_pack
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# -- Compiling entity alu
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# -- Compiling architecture logic of alu
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# Model Technology ModelSim SE vcom 6.0d Compiler 2005.04 Apr 25 2005
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# -- Loading package standard
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# -- Loading package std_logic_1164
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# -- Loading package mlite_pack
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# -- Compiling entity control
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# -- Compiling architecture logic of control
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# Model Technology ModelSim SE vcom 6.0d Compiler 2005.04 Apr 25 2005
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# -- Loading package standard
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# -- Loading package std_logic_1164
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# -- Loading package mlite_pack
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# -- Compiling entity mem_ctrl
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# -- Compiling architecture logic of mem_ctrl
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# Model Technology ModelSim SE vcom 6.0d Compiler 2005.04 Apr 25 2005
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# -- Loading package standard
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# -- Loading package std_logic_1164
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# -- Loading package std_logic_arith
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# -- Loading package std_logic_unsigned
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# -- Loading package mlite_pack
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# -- Compiling entity mult
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# -- Compiling architecture logic of mult
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# Model Technology ModelSim SE vcom 6.0d Compiler 2005.04 Apr 25 2005
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# -- Loading package standard
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# -- Loading package std_logic_1164
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# -- Loading package mlite_pack
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# -- Compiling entity shifter
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# -- Compiling architecture logic of shifter
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# Model Technology ModelSim SE vcom 6.0d Compiler 2005.04 Apr 25 2005
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# -- Loading package standard
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# -- Loading package std_logic_1164
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# -- Loading package mlite_pack
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# -- Compiling entity bus_mux
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# -- Compiling architecture logic of bus_mux
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# Model Technology ModelSim SE vcom 6.0d Compiler 2005.04 Apr 25 2005
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# -- Loading package standard
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# -- Loading package std_logic_1164
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# -- Loading package std_logic_arith
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# -- Loading package std_logic_unsigned
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# -- Loading package mlite_pack
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# -- Compiling entity ddr_ctrl
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# -- Compiling architecture logic of ddr_ctrl
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# Model Technology ModelSim SE vcom 6.0d Compiler 2005.04 Apr 25 2005
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# -- Loading package standard
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# -- Loading package std_logic_1164
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# -- Loading package mlite_pack
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# -- Loading package std_logic_arith
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# -- Loading package std_logic_unsigned
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# -- Compiling entity mlite_cpu
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# -- Compiling architecture logic of mlite_cpu
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# Model Technology ModelSim SE vcom 6.0d Compiler 2005.04 Apr 25 2005
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# -- Loading package standard
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# -- Loading package std_logic_1164
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# -- Loading package mlite_pack
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# -- Compiling entity pc_next
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# -- Compiling architecture logic of pc_next
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# Model Technology ModelSim SE vcom 6.0d Compiler 2005.04 Apr 25 2005
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# -- Loading package standard
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# -- Loading package std_logic_1164
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# -- Loading package std_logic_arith
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# -- Loading package std_logic_unsigned
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# -- Loading package vcomponents
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# -- Loading package mlite_pack
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# -- Compiling entity cache
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# -- Compiling architecture logic of cache
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# Model Technology ModelSim SE vcom 6.0d Compiler 2005.04 Apr 25 2005
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# -- Loading package standard
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# -- Loading package std_logic_1164
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# -- Loading package std_logic_arith
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# -- Loading package std_logic_unsigned
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# -- Loading package mlite_pack
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# -- Compiling entity eth_dma
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# -- Compiling architecture logic of eth_dma
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# Model Technology ModelSim SE vcom 6.0d Compiler 2005.04 Apr 25 2005
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# -- Loading package standard
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# -- Loading package std_logic_1164
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# -- Loading package mlite_pack
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# -- Compiling entity pipeline
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# -- Compiling architecture logic of pipeline
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# Model Technology ModelSim SE vcom 6.0d Compiler 2005.04 Apr 25 2005
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# -- Loading package standard
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# -- Loading package std_logic_1164
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# -- Loading package std_logic_arith
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# -- Loading package std_logic_unsigned
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# -- Loading package mlite_pack
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# -- Compiling entity reg_bank
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# -- Compiling architecture ram_block of reg_bank
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# Model Technology ModelSim SE vcom 6.0d Compiler 2005.04 Apr 25 2005
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# -- Loading package standard
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# -- Loading package std_logic_1164
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# -- Loading package attributes
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# -- Loading package std_logic_misc
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# -- Loading package std_logic_arith
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# -- Loading package textio
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# -- Loading package std_logic_textio
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# -- Loading package std_logic_unsigned
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# -- Loading package mlite_pack
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# -- Compiling entity uart
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# -- Compiling architecture logic of uart
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# Model Technology ModelSim SE vcom 6.0d Compiler 2005.04 Apr 25 2005
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# -- Loading package standard
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# -- Loading package std_logic_1164
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# -- Loading package std_logic_arith
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# -- Loading package std_logic_unsigned
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# -- Compiling entity plasma_3e
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# -- Compiling architecture logic of plasma_3e
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# Model Technology ModelSim SE vcom 6.0d Compiler 2005.04 Apr 25 2005
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# -- Loading package standard
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# -- Loading package std_logic_1164
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# -- Loading package attributes
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# -- Loading package std_logic_misc
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# -- Loading package std_logic_arith
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# -- Loading package std_logic_unsigned
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# -- Loading package mlite_pack
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# -- Loading package vcomponents
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# -- Compiling entity ram
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# -- Compiling architecture logic of ram
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# Model Technology ModelSim SE vcom 6.0d Compiler 2005.04 Apr 25 2005
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# -- Loading package standard
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# -- Loading package std_logic_1164
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# -- Loading package mlite_pack
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# -- Loading package std_logic_arith
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# -- Loading package std_logic_unsigned
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# -- Compiling entity tbench
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# -- Compiling architecture logic of tbench
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# vsim -t 1ps tbench
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# Loading /home/opt/cad/modeltech/linux/../std.standard
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# Loading /home/opt/cad/modeltech/linux/../ieee.std_logic_1164(body)
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# Loading work.mlite_pack(body)
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# Loading /home/opt/cad/modeltech/linux/../ieee.std_logic_arith(body)
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# Loading /home/opt/cad/modeltech/linux/../ieee.std_logic_unsigned(body)
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# Loading work.tbench(logic)
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# Loading work.plasma(logic)
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# Loading work.mlite_cpu(logic)
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# Loading work.pc_next(logic)
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# Loading work.mem_ctrl(logic)
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# Loading work.control(logic)
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# Loading work.reg_bank(ram_block)
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# Loading work.bus_mux(logic)
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# Loading work.alu(logic)
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# Loading work.shifter(logic)
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# Loading work.mult(logic)
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# Loading /opt/cad/modeltech/xilinx/vhdl/unisim.vcomponents
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# Loading work.cache(logic)
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# Loading /home/opt/cad/modeltech/linux/../synopsys.attributes
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# Loading /home/opt/cad/modeltech/linux/../ieee.std_logic_misc(body)
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# Loading work.ram(logic)
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# Loading /home/opt/cad/modeltech/linux/../std.textio(body)
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# Loading /home/opt/cad/modeltech/linux/../ieee.vital_timing(body)
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# Loading /home/opt/cad/modeltech/linux/../ieee.vital_primitives(body)
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# Loading /opt/cad/modeltech/xilinx/vhdl/unisim.vpkg(body)
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# Loading /opt/cad/modeltech/xilinx/vhdl/unisim.ramb16_s9(ramb16_s9_v)
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# Loading /home/opt/cad/modeltech/linux/../ieee.std_logic_textio(body)
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# Loading work.uart(logic)
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# Loading work.eth_dma(logic)
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# .main_pane.mdi.interior.cs.vm.paneset.cli_0.wf.clip.cs
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# .main_pane.workspace
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# .main_pane.signals.interior.cs
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# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
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# Time: 0 ps Iteration: 0 Instance: /tbench
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# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0.
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# Time: 0 ps Iteration: 0 Instance: /tbench
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# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
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# Time: 0 ps Iteration: 0 Instance: /tbench/u1_plasma/dma_gen2/u4_eth
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# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
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# Time: 0 ps Iteration: 0 Instance: /tbench/u1_plasma/dma_gen2/u4_eth
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# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
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# Time: 0 ps Iteration: 0 Instance: /tbench/u1_plasma/u3_uart
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# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
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# Time: 0 ps Iteration: 0 Instance: /tbench/u1_plasma/opt_cache2/u_cache
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# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
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# Time: 0 ps Iteration: 0 Instance: /tbench/u1_plasma/opt_cache2/u_cache
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# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
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# Time: 0 ps Iteration: 0 Instance: /tbench/u1_plasma/opt_cache2/u_cache
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# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
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# Time: 0 ps Iteration: 0 Instance: /tbench/u1_plasma/u1_cpu/u8_mult
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# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
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# Time: 0 ps Iteration: 0 Instance: /tbench/u1_plasma/u1_cpu/u8_mult
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# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
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# Time: 0 ps Iteration: 0 Instance: /tbench/u1_plasma/u1_cpu/u8_mult
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# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
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# Time: 0 ps Iteration: 0 Instance: /tbench/u1_plasma/u1_cpu/u8_mult
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# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
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# Time: 0 ps Iteration: 0 Instance: /tbench/u1_plasma/u1_cpu/u8_mult
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# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
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# Time: 0 ps Iteration: 0 Instance: /tbench/u1_plasma/u1_cpu/u8_mult
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# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
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# Time: 0 ps Iteration: 0 Instance: /tbench/u1_plasma/u1_cpu/u4_reg_bank/tri_port_mem
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# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0.
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# Time: 0 ps Iteration: 0 Instance: /tbench/u1_plasma/u1_cpu/u4_reg_bank/tri_port_mem
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# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
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# Time: 0 ps Iteration: 0 Instance: /tbench/u1_plasma/u1_cpu/u4_reg_bank/tri_port_mem
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# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0.
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# Time: 0 ps Iteration: 0 Instance: /tbench/u1_plasma/u1_cpu/u4_reg_bank/tri_port_mem
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# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
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# Time: 0 ps Iteration: 0 Instance: /tbench/u1_plasma/u1_cpu/u4_reg_bank
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# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
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# Time: 0 ps Iteration: 0 Instance: /tbench/u1_plasma/u1_cpu/u4_reg_bank
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# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
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# Time: 0 ps Iteration: 0 Instance: /tbench/u1_plasma/u1_cpu/u4_reg_bank
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# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
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# Time: 0 ps Iteration: 0 Instance: /tbench/u1_plasma/u1_cpu/u4_reg_bank
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# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
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# Time: 0 ps Iteration: 0 Instance: /tbench/u1_plasma/u1_cpu
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# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
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# Time: 0 ps Iteration: 1 Instance: /tbench/u1_plasma/u1_cpu/u4_reg_bank/tri_port_mem
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# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0.
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# Time: 0 ps Iteration: 1 Instance: /tbench/u1_plasma/u1_cpu/u4_reg_bank/tri_port_mem
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# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
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# Time: 0 ps Iteration: 1 Instance: /tbench/u1_plasma/u1_cpu/u4_reg_bank/tri_port_mem
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# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0.
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# Time: 0 ps Iteration: 1 Instance: /tbench/u1_plasma/u1_cpu/u4_reg_bank/tri_port_mem
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# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
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# Time: 0 ps Iteration: 1 Instance: /tbench/u1_plasma/opt_cache2/u_cache
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# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
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# Time: 0 ps Iteration: 1 Instance: /tbench/u1_plasma/u1_cpu/u4_reg_bank
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# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
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# Time: 0 ps Iteration: 1 Instance: /tbench/u1_plasma/u1_cpu/u4_reg_bank
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# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
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# Time: 0 ps Iteration: 1 Instance: /tbench/u1_plasma/u1_cpu/u4_reg_bank
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# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
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# Time: 0 ps Iteration: 1 Instance: /tbench/u1_plasma/u1_cpu/u4_reg_bank
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# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
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# Time: 0 ps Iteration: 1 Instance: /tbench
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# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0.
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# Time: 0 ps Iteration: 1 Instance: /tbench
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# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
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# Time: 0 ps Iteration: 2 Instance: /tbench/u1_plasma/u1_cpu/u4_reg_bank
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# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
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# Time: 0 ps Iteration: 2 Instance: /tbench
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# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0.
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# Time: 0 ps Iteration: 2 Instance: /tbench
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# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
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# Time: 0 ps Iteration: 2 Instance: /tbench/u1_plasma/opt_cache2/u_cache
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# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
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# Time: 0 ps Iteration: 3 Instance: /tbench/u1_plasma/u1_cpu/u4_reg_bank/tri_port_mem
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# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0.
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# Time: 0 ps Iteration: 3 Instance: /tbench/u1_plasma/u1_cpu/u4_reg_bank/tri_port_mem
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# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
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# Time: 0 ps Iteration: 3 Instance: /tbench/u1_plasma/u1_cpu/u4_reg_bank/tri_port_mem
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# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0.
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# Time: 0 ps Iteration: 3 Instance: /tbench/u1_plasma/u1_cpu/u4_reg_bank/tri_port_mem
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# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
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# Time: 0 ps Iteration: 3 Instance: /tbench/u1_plasma/opt_cache2/u_cache
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# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
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# Time: 0 ps Iteration: 4 Instance: /tbench/u1_plasma/u1_cpu/u4_reg_bank/tri_port_mem
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# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0.
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# Time: 0 ps Iteration: 4 Instance: /tbench/u1_plasma/u1_cpu/u4_reg_bank/tri_port_mem
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# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
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# Time: 0 ps Iteration: 4 Instance: /tbench/u1_plasma/u1_cpu/u4_reg_bank/tri_port_mem
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# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0.
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# Time: 0 ps Iteration: 4 Instance: /tbench/u1_plasma/u1_cpu/u4_reg_bank/tri_port_mem
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# Break key hit
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# Simulation stop requested.
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