mirror of
git://projects.qi-hardware.com/nn-usb-fpga.git
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105 lines
3.2 KiB
Verilog
105 lines
3.2 KiB
Verilog
`timescale 1ns / 1ps
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module ADC(clk, sram_data, addr, nwe, ncs, noe, reset, led, ADC_EOC,
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ADC_SCLK, ADC_SDIN, ADC_SDOUT, ADC_CS, ADC_CSTART);
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parameter B = (7);
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input clk, addr, nwe, ncs, noe, reset, ADC_EOC;
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inout [B:0] sram_data;
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output led, ADC_CS, ADC_CSTART, ADC_SCLK;
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inout ADC_SDIN, ADC_SDOUT;
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// Internal conection
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reg led;
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// synchronize signals
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reg sncs, snwe;
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reg [10:0] buffer_addr;
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wire [8:0] addr2;
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reg [B:0] buffer_data;
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// interfaz fpga signals
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wire [10:0] addr;
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// bram interfaz signals
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reg we;
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wire we2;
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reg w_st=0;
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reg [B:0] wrBus;
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wire [B:0] rdBus;
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wire [B:0] wrBus2;
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wire [B:0] rdBus2;
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reg [25:0] counter;
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// Test : LED blinking
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always @(posedge clk) begin
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if (reset)
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counter <= {25{1'b0}};
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else
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counter <= counter + 1;
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led <=counter[25];
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end
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// interefaz signals assignments
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wire T = ~noe | ncs;
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assign sram_data = T?8'bZ:rdBus;
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// synchronize assignment
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always @(negedge clk)
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begin
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sncs <= ncs;
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snwe <= nwe;
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buffer_data <= sram_data;
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buffer_addr <= addr;
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end
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// write access cpu to bram
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always @(posedge clk)
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if(reset) {w_st, we, wrBus} <= 0;
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else begin
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wrBus <= buffer_data;
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case (w_st)
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0: begin
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we <= 0;
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if(sncs | snwe) w_st <= 1;
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end
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1: begin
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if(~(sncs | snwe)) begin
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we <= 1;
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w_st <= 0;
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end
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else we <= 0;
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end
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endcase
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end
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// Dual-port RAM instatiation
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RAMB16_S9_S9 ba0(
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.DOA(rdBus), // Port A 8-bit Data Output
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.DOB(rdBus2), // Port B 8-bit Data Output
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.DOPA(), // Port A 1-bit Parity Output
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.DOPB(), // Port B 1-bit Parity Output
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.ADDRA(buffer_addr[10:0]), // Port A 11-bit Address Input
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.ADDRB(addr2[8:0]), // Port B 11-bit Address Input
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.CLKA(~clk), // Port A Clock
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.CLKB(~clk), // Port B Clock
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.DIA(wrBus), // Port A 8-bit Data Input
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.DIB(wrBus2), // Port B 8-bit Data Input
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.DIPA(1'b0), // Port A 1-bit parity Input
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.DIPB(1'b0), // Port-B 1-bit parity Input
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.ENA(1'b1), // Port A RAM Enable Input
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.ENB(1'b1), // Port B RAM Enable Input
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.SSRA(1'b0), // Port A Synchronous Set/Reset Input
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.SSRB(1'b0), // Port B Synchronous Set/Reset Input
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.WEA(we), // Port A Write Enable Input
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.WEB(we2) ); // Port B Write Enable Input
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// Peripheral instantiation
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ADC_peripheral P1( clk, reset, ADC_EOC, ADC_CS, ADC_CSTART,
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ADC_SCLK, ADC_SDIN, ADC_SDOUT, we2,
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rdBus2, wrBus2, addr2);
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endmodule
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