mirror of
git://projects.qi-hardware.com/nn-usb-fpga.git
synced 2025-01-23 11:11:06 +02:00
Adding ADC example
This commit is contained in:
Carlos Camargo
parent
34b8cb651b
commit
0b5d03e1e6
41
Examples/ADC/logic/ADC.ucf
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41
Examples/ADC/logic/ADC.ucf
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NET clk LOC = "P38";
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NET reset LOC = "P71"; #WARNING change to another pin
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NET led LOC = "P44";
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#ADDRESS BUS
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#NET "addr<12>" LOC = "P90";
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#NET "addr<11>" LOC = "P91";
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NET "addr<10>" LOC = "P85";
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NET "addr<9>" LOC = "P92";
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NET "addr<8>" LOC = "P94";
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NET "addr<7>" LOC = "P95";
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NET "addr<6>" LOC = "P98";
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NET "addr<5>" LOC = "P3";
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NET "addr<4>" LOC = "P2";
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NET "addr<3>" LOC = "P78";
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NET "addr<2>" LOC = "P79";
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NET "addr<1>" LOC = "P83";
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NET "addr<0>" LOC = "P84";
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#DATA BUS
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NET "sram_data<7>" LOC = "P4";
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NET "sram_data<6>" LOC = "P5";
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NET "sram_data<5>" LOC = "P9";
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NET "sram_data<4>" LOC = "P10";
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NET "sram_data<3>" LOC = "P11";
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NET "sram_data<2>" LOC = "P12";
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NET "sram_data<1>" LOC = "P15";
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NET "sram_data<0>" LOC = "P16";
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#CONTROL BUS
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NET "nwe" LOC = "P88";
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NET "noe" LOC = "P86";
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NET "ncs" LOC = "P69";
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#ADC
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NET "ADC_EOC" LOC = "P17";
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NET "ADC_SCLK" LOC = "P18" ;
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NET "ADC_SDIN" LOC = "P22";
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NET "ADC_SDOUT" LOC = "P23";
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NET "ADC_CS" LOC = "P24";
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NET "ADC_CSTART" LOC = "P26";
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104
Examples/ADC/logic/ADC.v
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104
Examples/ADC/logic/ADC.v
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`timescale 1ns / 1ps
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module ADC(clk, sram_data, addr, nwe, ncs, noe, reset, led, ADC_EOC,
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ADC_SCLK, ADC_SDIN, ADC_SDOUT, ADC_CS, ADC_CSTART);
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parameter B = (7);
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input clk, addr, nwe, ncs, noe, reset, ADC_EOC;
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inout [B:0] sram_data;
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output led, ADC_CS, ADC_CSTART, ADC_SCLK;
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inout ADC_SDIN, ADC_SDOUT;
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// Internal conection
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reg led;
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// synchronize signals
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reg sncs, snwe;
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reg [10:0] buffer_addr;
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wire [8:0] addr2;
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reg [B:0] buffer_data;
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// interfaz fpga signals
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wire [10:0] addr;
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// bram interfaz signals
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reg we;
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wire we2;
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reg w_st=0;
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reg [B:0] wrBus;
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wire [B:0] rdBus;
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wire [B:0] wrBus2;
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wire [B:0] rdBus2;
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reg [25:0] counter;
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// Test : LED blinking
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always @(posedge clk) begin
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if (reset)
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counter <= {25{1'b0}};
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else
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counter <= counter + 1;
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led <=counter[25];
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end
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// interefaz signals assignments
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wire T = ~noe | ncs;
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assign sram_data = T?8'bZ:rdBus;
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// synchronize assignment
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always @(negedge clk)
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begin
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sncs <= ncs;
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snwe <= nwe;
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buffer_data <= sram_data;
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buffer_addr <= addr;
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end
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// write access cpu to bram
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always @(posedge clk)
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if(reset) {w_st, we, wrBus} <= 0;
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else begin
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wrBus <= buffer_data;
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case (w_st)
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0: begin
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we <= 0;
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if(sncs | snwe) w_st <= 1;
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end
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1: begin
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if(~(sncs | snwe)) begin
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we <= 1;
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w_st <= 0;
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end
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else we <= 0;
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end
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endcase
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end
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// Dual-port RAM instatiation
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RAMB16_S9_S9 ba0(
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.DOA(rdBus), // Port A 8-bit Data Output
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.DOB(rdBus2), // Port B 8-bit Data Output
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.DOPA(), // Port A 1-bit Parity Output
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.DOPB(), // Port B 1-bit Parity Output
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.ADDRA(buffer_addr[10:0]), // Port A 11-bit Address Input
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.ADDRB(addr2[8:0]), // Port B 11-bit Address Input
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.CLKA(~clk), // Port A Clock
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.CLKB(~clk), // Port B Clock
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.DIA(wrBus), // Port A 8-bit Data Input
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.DIB(wrBus2), // Port B 8-bit Data Input
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.DIPA(1'b0), // Port A 1-bit parity Input
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.DIPB(1'b0), // Port-B 1-bit parity Input
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.ENA(1'b1), // Port A RAM Enable Input
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.ENB(1'b1), // Port B RAM Enable Input
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.SSRA(1'b0), // Port A Synchronous Set/Reset Input
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.SSRB(1'b0), // Port B Synchronous Set/Reset Input
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.WEA(we), // Port A Write Enable Input
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.WEB(we2) ); // Port B Write Enable Input
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// Peripheral instantiation
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ADC_peripheral P1( clk, reset, ADC_EOC, ADC_CS, ADC_CSTART,
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ADC_SCLK, ADC_SDIN, ADC_SDOUT, we2,
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rdBus2, wrBus2, addr2);
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endmodule
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161
Examples/ADC/logic/ADC_peripheral.v
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161
Examples/ADC/logic/ADC_peripheral.v
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@ -0,0 +1,161 @@
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`timescale 1ns / 1ps
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module ADC_peripheral( clk, reset, ADC_EOC, ADC_CS, ADC_CSTART,
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ADC_SCLK, ADC_SDIN, ADC_SDOUT, we2,
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rdBus2, wrBus2, addr2);
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input clk, reset, ADC_EOC;
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input [7:0] rdBus2;
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output we2, ADC_CS, ADC_CSTART, ADC_SCLK;
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output [7:0] wrBus2;
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output [8:0] addr2;
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inout ADC_SDIN, ADC_SDOUT;
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reg we2=0, nSample=0;
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reg [7:0] wrBus2;
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reg [8:0] addr2;
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reg [7:0] auto_count=0;
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reg [4:0] w_st2=0;
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reg [3:0] SPI_in_data=0;
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reg [9:0] SPI_out_data;
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reg SPI_rd = 0;
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reg SPI_wr = 0;
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reg [7:0] buffer_rd1;
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reg [3:0] ADC_cmd;
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assign ADC_CSTART = 1'b1;
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// SPI comunication module instantiation
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reg ADC_SCLK_buffer = 0;
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reg ADC_SDIN_buffer = 0;
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reg busy = 0;
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reg [3:0] in_buffer=0;
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reg [9:0] out_buffer;
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reg [7:0] clkcount = 0;
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reg [7:0] clkdiv = 255;
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reg [4:0] count = 0;
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assign ADC_CS = ~busy;
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always@(SPI_rd or out_buffer or busy or clkdiv)
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begin
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SPI_out_data = 10'bx;
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if(SPI_rd)
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begin SPI_out_data = out_buffer; end
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end
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always@(negedge clk)
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begin
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if(!busy)
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begin
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if(SPI_wr)
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begin in_buffer = SPI_in_data; busy = 1; end
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end
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else
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begin
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clkcount = clkcount + 1;
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if(clkcount >= clkdiv)
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begin
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clkcount = 0;
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// Send the ADC CMD on first 4 rising edge of SCLK
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if((count % 2) == 0)
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begin
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ADC_SDIN_buffer = in_buffer[3];
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in_buffer = in_buffer << 1;
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end
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// We generate 10 cicles of SCLK
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if(count > 0 && count < 21)
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begin
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ADC_SCLK_buffer = ~ADC_SCLK_buffer;
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end
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count = count + 1;
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if(count > 21)
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begin
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count = 0;
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busy = 0;
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end
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end
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end
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end
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always@(posedge ADC_SCLK_buffer)
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begin
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out_buffer = out_buffer << 1;
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out_buffer[0] = ADC_SDOUT;
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end
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assign ADC_SCLK = ADC_SCLK_buffer;
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assign ADC_SDIN = ADC_SDIN_buffer;
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// State Machine for control ADC comunication
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always @(posedge clk)
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if(reset)
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{we2, SPI_wr, SPI_rd, w_st2, auto_count, SPI_in_data} <= 0;
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else begin
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case (w_st2)
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0: begin addr2 <= 0; w_st2 <= 1; end
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1: begin
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ADC_cmd <= rdBus2[3:0];
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if (rdBus2[7:4] == 5)
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// Send command without read samples
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begin addr2<= 2; w_st2 <= 2; nSample <= 1; end
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else if (rdBus2[7:4] == 6)
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// Read: Stop when buffer full
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begin addr2<= 2; w_st2 <= 2; nSample <= 0; end
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else if (rdBus2[7:4] == 9)
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// Set clkdiv on SPI controller
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begin addr2<= 1; w_st2 <= 10; end
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else
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begin w_st2 <= 0; end
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end
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2: begin
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if (rdBus2[7:0] == 0)
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begin auto_count<=0; w_st2 <= 0; end
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else begin
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//Send data to ADC
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buffer_rd1<=rdBus2;
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auto_count<=auto_count+1;
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SPI_in_data <= ADC_cmd[3:0];
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SPI_wr <= 1; w_st2 <= 3;
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end
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end
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3: begin
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SPI_wr <= 0;
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//Wait for complete convertion
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if(!ADC_EOC || ADC_CS) begin
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buffer_rd1<=buffer_rd1-1;
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SPI_rd <=1;
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if(nSample)
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w_st2<= 8;
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else
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w_st2<= 4;
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end
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end
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4: begin
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//Write data on BRAM (LOW)
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wrBus2 <= SPI_out_data[7:0];
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addr2 <= 2+2*auto_count;
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we2 <= 1; w_st2 <= 5;
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end
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5: begin we2 <= 0; w_st2 <= 6; end
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6: begin
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//Write data on BRAM (HI)
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wrBus2 <= SPI_out_data[9:8];
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addr2 <= 3+2*auto_count;
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we2 <= 1; w_st2 <= 7;
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end
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7: begin we2 <= 0; w_st2 <= 8; end
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8: begin
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SPI_rd <=0;
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//Update Buffer Size value
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wrBus2 <= buffer_rd1;
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addr2 <= 2;
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we2 <= 1; w_st2 <= 9;
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end
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9: begin we2 <= 0; w_st2 <= 0; end
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//Sent clock divider for speed on SPI comunication
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10: begin clkdiv = rdBus2; w_st2 <= 0; end
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endcase
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end
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endmodule
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74
Examples/ADC/logic/Makefile
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74
Examples/ADC/logic/Makefile
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DESIGN = ADC
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PINS = $(DESIGN).ucf
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DEVICE = xc3s250e-VQ100-4
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BGFLAGS = -g TdoPin:PULLNONE -g DonePin:PULLUP \
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-g CRC:enable -g StartUpClk:CCLK
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SIM_CMD = /opt/cad/modeltech/bin/vsim
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SIM_COMP_SCRIPT = simulation/$(DESIGN)_TB.do
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#SIM_INIT_SCRIPT = simulation/$(DESIGN)_init.do
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SIMGEN_OPTIONS = -p $(FPGA_ARCH) -lang $(LANGUAGE)
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SAKC_IP = 192.168.254.101
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SRC = $(DESIGN).v ADC_peripheral.v
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all: bits
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remake: clean-build all
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clean:
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rm -f *~ */*~ a.out *.log *.key *.edf *.ps trace.dat
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rm *.bit
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clean-build: clean
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rm -rf build
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cleanall: clean
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rm -rf build $(DESIGN).bit
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bits: $(DESIGN).bit
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#
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# Synthesis
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#
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build/project.src:
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@[ -d build ] || mkdir build
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@rm -f $@
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for i in $(SRC); do echo verilog work ../$$i >> $@; done
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for i in $(SRC_HDL); do echo VHDL work ../$$i >> $@; done
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build/project.xst: build/project.src
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echo "run" > $@
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echo "-top $(DESIGN) " >> $@
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echo "-p $(DEVICE)" >> $@
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echo "-opt_mode Area" >> $@
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echo "-opt_level 1" >> $@
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echo "-ifn project.src" >> $@
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echo "-ifmt mixed" >> $@
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echo "-ofn project.ngc" >> $@
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echo "-ofmt NGC" >> $@
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echo "-rtlview yes" >> $@
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build/project.ngc: build/project.xst $(SRC)
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cd build && xst -ifn project.xst -ofn project.log
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build/project.ngd: build/project.ngc $(PINS)
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cd build && ngdbuild -p $(DEVICE) project.ngc -uc ../$(PINS)
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build/project.ncd: build/project.ngd
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cd build && map -pr b -p $(DEVICE) project
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build/project_r.ncd: build/project.ncd
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cd build && par -w project project_r.ncd
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build/project_r.twr: build/project_r.ncd
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cd build && trce -v 25 project_r.ncd project.pcf
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$(DESIGN).bit: build/project_r.ncd build/project_r.twr
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cd build && bitgen project_r.ncd -l -w $(BGFLAGS)
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@mv -f build/project_r.bit $@
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sim:
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cd simulation; $(SIM_CMD) -do $(DESIGN)_TB.do
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upload: $(DESIGN).bit
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scp $(DESIGN).bit root@$(SAKC_IP):
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