mirror of
git://projects.qi-hardware.com/nn-usb-fpga.git
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ea03c86992
Change Y3 footprint Change D10 footprint Remove J18, Using J17 circuit for switch between USB and DC plug power supply, this remove the possibility that the USB host will be connected to DC wall adapter. Change L13 footprint
539 lines
22 KiB
VHDL
539 lines
22 KiB
VHDL
---------------------------------------------------------------------
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-- TITLE: Plasma Misc. Package
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-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
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-- DATE CREATED: 2/15/01
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-- FILENAME: mlite_pack.vhd
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-- PROJECT: Plasma CPU core
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-- COPYRIGHT: Software placed into the public domain by the author.
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-- Software 'as is' without warranty. Author liable for nothing.
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-- DESCRIPTION:
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-- Data types, constants, and add functions needed for the Plasma CPU.
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---------------------------------------------------------------------
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library ieee;
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use ieee.numeric_std.all;
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use ieee.std_logic_1164.all;
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package mlite_pack is
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constant ZERO : std_logic_vector(31 downto 0) :=
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"00000000000000000000000000000000";
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constant ONES : std_logic_vector(31 downto 0) :=
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"11111111111111111111111111111111";
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--make HIGH_Z equal to ZERO if compiler complains
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constant HIGH_Z : std_logic_vector(31 downto 0) :=
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"ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
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subtype alu_function_type is std_logic_vector(3 downto 0);
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constant ALU_NOTHING : alu_function_type := "0000";
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constant ALU_ADD : alu_function_type := "0001";
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constant ALU_SUBTRACT : alu_function_type := "0010";
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constant ALU_LESS_THAN : alu_function_type := "0011";
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constant ALU_LESS_THAN_SIGNED : alu_function_type := "0100";
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constant ALU_OR : alu_function_type := "0101";
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constant ALU_AND : alu_function_type := "0110";
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constant ALU_XOR : alu_function_type := "0111";
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constant ALU_NOR : alu_function_type := "1000";
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subtype shift_function_type is std_logic_vector(1 downto 0);
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constant SHIFT_NOTHING : shift_function_type := "00";
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constant SHIFT_LEFT_UNSIGNED : shift_function_type := "01";
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constant SHIFT_RIGHT_SIGNED : shift_function_type := "11";
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constant SHIFT_RIGHT_UNSIGNED : shift_function_type := "10";
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subtype mult_function_type is std_logic_vector(3 downto 0);
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constant MULT_NOTHING : mult_function_type := "0000";
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constant MULT_READ_LO : mult_function_type := "0001";
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constant MULT_READ_HI : mult_function_type := "0010";
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constant MULT_WRITE_LO : mult_function_type := "0011";
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constant MULT_WRITE_HI : mult_function_type := "0100";
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constant MULT_MULT : mult_function_type := "0101";
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constant MULT_SIGNED_MULT : mult_function_type := "0110";
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constant MULT_DIVIDE : mult_function_type := "0111";
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constant MULT_SIGNED_DIVIDE : mult_function_type := "1000";
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subtype a_source_type is std_logic_vector(1 downto 0);
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constant A_FROM_REG_SOURCE : a_source_type := "00";
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constant A_FROM_IMM10_6 : a_source_type := "01";
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constant A_FROM_PC : a_source_type := "10";
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subtype b_source_type is std_logic_vector(1 downto 0);
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constant B_FROM_REG_TARGET : b_source_type := "00";
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constant B_FROM_IMM : b_source_type := "01";
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constant B_FROM_SIGNED_IMM : b_source_type := "10";
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constant B_FROM_IMMX4 : b_source_type := "11";
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subtype c_source_type is std_logic_vector(2 downto 0);
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constant C_FROM_NULL : c_source_type := "000";
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constant C_FROM_ALU : c_source_type := "001";
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constant C_FROM_SHIFT : c_source_type := "001"; --same as alu
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constant C_FROM_MULT : c_source_type := "001"; --same as alu
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constant C_FROM_MEMORY : c_source_type := "010";
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constant C_FROM_PC : c_source_type := "011";
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constant C_FROM_PC_PLUS4 : c_source_type := "100";
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constant C_FROM_IMM_SHIFT16: c_source_type := "101";
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constant C_FROM_REG_SOURCEN: c_source_type := "110";
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subtype pc_source_type is std_logic_vector(1 downto 0);
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constant FROM_INC4 : pc_source_type := "00";
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constant FROM_OPCODE25_0 : pc_source_type := "01";
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constant FROM_BRANCH : pc_source_type := "10";
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constant FROM_LBRANCH : pc_source_type := "11";
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subtype branch_function_type is std_logic_vector(2 downto 0);
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constant BRANCH_LTZ : branch_function_type := "000";
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constant BRANCH_LEZ : branch_function_type := "001";
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constant BRANCH_EQ : branch_function_type := "010";
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constant BRANCH_NE : branch_function_type := "011";
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constant BRANCH_GEZ : branch_function_type := "100";
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constant BRANCH_GTZ : branch_function_type := "101";
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constant BRANCH_YES : branch_function_type := "110";
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constant BRANCH_NO : branch_function_type := "111";
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-- mode(32=1,16=2,8=3), signed, write
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subtype mem_source_type is std_logic_vector(3 downto 0);
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constant MEM_FETCH : mem_source_type := "0000";
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constant MEM_READ32 : mem_source_type := "0100";
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constant MEM_WRITE32 : mem_source_type := "0101";
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constant MEM_READ16 : mem_source_type := "1000";
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constant MEM_READ16S : mem_source_type := "1010";
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constant MEM_WRITE16 : mem_source_type := "1001";
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constant MEM_READ8 : mem_source_type := "1100";
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constant MEM_READ8S : mem_source_type := "1110";
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constant MEM_WRITE8 : mem_source_type := "1101";
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function bv_adder(a : in std_logic_vector;
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b : in std_logic_vector;
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do_add: in std_logic) return std_logic_vector;
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function bv_negate(a : in std_logic_vector) return std_logic_vector;
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function bv_increment(a : in std_logic_vector(31 downto 2)
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) return std_logic_vector;
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function bv_inc(a : in std_logic_vector
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) return std_logic_vector;
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-- For Altera
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COMPONENT lpm_ram_dp
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generic (
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LPM_WIDTH : natural; -- MUST be greater than 0
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LPM_WIDTHAD : natural; -- MUST be greater than 0
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LPM_NUMWORDS : natural := 0;
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LPM_INDATA : string := "REGISTERED";
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LPM_OUTDATA : string := "REGISTERED";
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LPM_RDADDRESS_CONTROL : string := "REGISTERED";
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LPM_WRADDRESS_CONTROL : string := "REGISTERED";
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LPM_FILE : string := "UNUSED";
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LPM_TYPE : string := "LPM_RAM_DP";
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USE_EAB : string := "OFF";
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INTENDED_DEVICE_FAMILY : string := "UNUSED";
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RDEN_USED : string := "TRUE";
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LPM_HINT : string := "UNUSED");
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port (
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RDCLOCK : in std_logic := '0';
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RDCLKEN : in std_logic := '1';
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RDADDRESS : in std_logic_vector(LPM_WIDTHAD-1 downto 0);
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RDEN : in std_logic := '1';
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DATA : in std_logic_vector(LPM_WIDTH-1 downto 0);
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WRADDRESS : in std_logic_vector(LPM_WIDTHAD-1 downto 0);
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WREN : in std_logic;
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WRCLOCK : in std_logic := '0';
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WRCLKEN : in std_logic := '1';
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Q : out std_logic_vector(LPM_WIDTH-1 downto 0));
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END COMPONENT;
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-- For Altera
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component LPM_RAM_DQ
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generic (
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LPM_WIDTH : natural; -- MUST be greater than 0
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LPM_WIDTHAD : natural; -- MUST be greater than 0
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LPM_NUMWORDS : natural := 0;
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LPM_INDATA : string := "REGISTERED";
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LPM_ADDRESS_CONTROL: string := "REGISTERED";
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LPM_OUTDATA : string := "REGISTERED";
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LPM_FILE : string := "UNUSED";
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LPM_TYPE : string := "LPM_RAM_DQ";
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USE_EAB : string := "OFF";
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INTENDED_DEVICE_FAMILY : string := "UNUSED";
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LPM_HINT : string := "UNUSED");
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port (
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DATA : in std_logic_vector(LPM_WIDTH-1 downto 0);
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ADDRESS : in std_logic_vector(LPM_WIDTHAD-1 downto 0);
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INCLOCK : in std_logic := '0';
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OUTCLOCK : in std_logic := '0';
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WE : in std_logic;
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Q : out std_logic_vector(LPM_WIDTH-1 downto 0));
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end component;
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-- For Xilinx
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component RAM16X1D
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-- synthesis translate_off
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generic (INIT : bit_vector := X"16");
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-- synthesis translate_on
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port (DPO : out STD_ULOGIC;
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SPO : out STD_ULOGIC;
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A0 : in STD_ULOGIC;
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A1 : in STD_ULOGIC;
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A2 : in STD_ULOGIC;
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A3 : in STD_ULOGIC;
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D : in STD_ULOGIC;
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DPRA0 : in STD_ULOGIC;
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DPRA1 : in STD_ULOGIC;
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DPRA2 : in STD_ULOGIC;
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DPRA3 : in STD_ULOGIC;
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WCLK : in STD_ULOGIC;
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WE : in STD_ULOGIC);
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end component;
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component pc_next
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port(clk : in std_logic;
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reset_in : in std_logic;
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pc_new : in std_logic_vector(31 downto 2);
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take_branch : in std_logic;
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pause_in : in std_logic;
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opcode25_0 : in std_logic_vector(25 downto 0);
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pc_source : in pc_source_type;
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pc_future : out std_logic_vector(31 downto 2);
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pc_current : out std_logic_vector(31 downto 2);
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pc_plus4 : out std_logic_vector(31 downto 2));
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end component;
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component mem_ctrl
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port(clk : in std_logic;
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reset_in : in std_logic;
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pause_in : in std_logic;
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nullify_op : in std_logic;
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address_pc : in std_logic_vector(31 downto 2);
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opcode_out : out std_logic_vector(31 downto 0);
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address_in : in std_logic_vector(31 downto 0);
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mem_source : in mem_source_type;
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data_write : in std_logic_vector(31 downto 0);
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data_read : out std_logic_vector(31 downto 0);
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pause_out : out std_logic;
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address_next : out std_logic_vector(31 downto 2);
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byte_we_next : out std_logic_vector(3 downto 0);
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address : out std_logic_vector(31 downto 2);
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byte_we : out std_logic_vector(3 downto 0);
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data_w : out std_logic_vector(31 downto 0);
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data_r : in std_logic_vector(31 downto 0));
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end component;
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component control
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port(opcode : in std_logic_vector(31 downto 0);
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intr_signal : in std_logic;
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rs_index : out std_logic_vector(5 downto 0);
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rt_index : out std_logic_vector(5 downto 0);
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rd_index : out std_logic_vector(5 downto 0);
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imm_out : out std_logic_vector(15 downto 0);
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alu_func : out alu_function_type;
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shift_func : out shift_function_type;
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mult_func : out mult_function_type;
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branch_func : out branch_function_type;
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a_source_out : out a_source_type;
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b_source_out : out b_source_type;
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c_source_out : out c_source_type;
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pc_source_out: out pc_source_type;
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mem_source_out:out mem_source_type;
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exception_out: out std_logic);
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end component;
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component reg_bank
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generic(memory_type : string := "XILINX_16X");
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port(clk : in std_logic;
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reset_in : in std_logic;
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pause : in std_logic;
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rs_index : in std_logic_vector(5 downto 0);
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rt_index : in std_logic_vector(5 downto 0);
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rd_index : in std_logic_vector(5 downto 0);
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reg_source_out : out std_logic_vector(31 downto 0);
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reg_target_out : out std_logic_vector(31 downto 0);
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reg_dest_new : in std_logic_vector(31 downto 0);
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intr_enable : out std_logic);
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end component;
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component bus_mux
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port(imm_in : in std_logic_vector(15 downto 0);
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reg_source : in std_logic_vector(31 downto 0);
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a_mux : in a_source_type;
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a_out : out std_logic_vector(31 downto 0);
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reg_target : in std_logic_vector(31 downto 0);
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b_mux : in b_source_type;
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b_out : out std_logic_vector(31 downto 0);
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c_bus : in std_logic_vector(31 downto 0);
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c_memory : in std_logic_vector(31 downto 0);
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c_pc : in std_logic_vector(31 downto 2);
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c_pc_plus4 : in std_logic_vector(31 downto 2);
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c_mux : in c_source_type;
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reg_dest_out : out std_logic_vector(31 downto 0);
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branch_func : in branch_function_type;
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take_branch : out std_logic);
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end component;
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component alu
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generic(alu_type : string := "DEFAULT");
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port(a_in : in std_logic_vector(31 downto 0);
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b_in : in std_logic_vector(31 downto 0);
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alu_function : in alu_function_type;
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c_alu : out std_logic_vector(31 downto 0));
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end component;
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component shifter
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generic(shifter_type : string := "DEFAULT" );
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port(value : in std_logic_vector(31 downto 0);
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shift_amount : in std_logic_vector(4 downto 0);
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shift_func : in shift_function_type;
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c_shift : out std_logic_vector(31 downto 0));
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end component;
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component mult
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generic(mult_type : string := "DEFAULT");
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port(clk : in std_logic;
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reset_in : in std_logic;
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a, b : in std_logic_vector(31 downto 0);
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mult_func : in mult_function_type;
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c_mult : out std_logic_vector(31 downto 0);
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pause_out : out std_logic);
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end component;
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component pipeline
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port(clk : in std_logic;
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reset : in std_logic;
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a_bus : in std_logic_vector(31 downto 0);
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a_busD : out std_logic_vector(31 downto 0);
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b_bus : in std_logic_vector(31 downto 0);
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b_busD : out std_logic_vector(31 downto 0);
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alu_func : in alu_function_type;
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alu_funcD : out alu_function_type;
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shift_func : in shift_function_type;
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shift_funcD : out shift_function_type;
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mult_func : in mult_function_type;
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mult_funcD : out mult_function_type;
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reg_dest : in std_logic_vector(31 downto 0);
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reg_destD : out std_logic_vector(31 downto 0);
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rd_index : in std_logic_vector(5 downto 0);
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rd_indexD : out std_logic_vector(5 downto 0);
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rs_index : in std_logic_vector(5 downto 0);
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rt_index : in std_logic_vector(5 downto 0);
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pc_source : in pc_source_type;
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mem_source : in mem_source_type;
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a_source : in a_source_type;
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b_source : in b_source_type;
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c_source : in c_source_type;
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c_bus : in std_logic_vector(31 downto 0);
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pause_any : in std_logic;
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pause_pipeline : out std_logic);
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end component;
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component mlite_cpu
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generic(memory_type : string := "XILINX_16X"; --ALTERA_LPM, or DUAL_PORT_
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mult_type : string := "DEFAULT";
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shifter_type : string := "DEFAULT";
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alu_type : string := "DEFAULT";
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pipeline_stages : natural := 2); --2 or 3
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port(clk : in std_logic;
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reset_in : in std_logic;
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intr_in : in std_logic;
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address_next : out std_logic_vector(31 downto 2); --for synch ram
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byte_we_next : out std_logic_vector(3 downto 0);
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address : out std_logic_vector(31 downto 2);
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byte_we : out std_logic_vector(3 downto 0);
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data_w : out std_logic_vector(31 downto 0);
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data_r : in std_logic_vector(31 downto 0);
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mem_pause : in std_logic);
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end component;
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component cache
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generic(memory_type : string := "DEFAULT");
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port(clk : in std_logic;
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reset : in std_logic;
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address_next : in std_logic_vector(31 downto 2);
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byte_we_next : in std_logic_vector(3 downto 0);
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cpu_address : in std_logic_vector(31 downto 2);
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mem_busy : in std_logic;
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cache_check : out std_logic; --Stage1: address_next in first 2MB DDR
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cache_checking : out std_logic; --Stage2: cache checking
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cache_miss : out std_logic); --Stage2-3: cache miss
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end component; --cache
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component ram
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generic(memory_type : string := "DEFAULT");
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port(clk : in std_logic;
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enable : in std_logic;
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write_byte_enable : in std_logic_vector(3 downto 0);
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address : in std_logic_vector(31 downto 2);
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data_write : in std_logic_vector(31 downto 0);
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data_read : out std_logic_vector(31 downto 0));
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end component; --ram
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component uart
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generic(log_file : string := "UNUSED");
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port(clk : in std_logic;
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reset : in std_logic;
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cs : in std_logic;
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nRdWr : in std_logic;
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data_in : in std_logic_vector(7 downto 0);
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data_out : out std_logic_vector(7 downto 0);
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uart_read : in std_logic;
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uart_write : out std_logic;
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busy_write : out std_logic;
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data_avail : out std_logic);
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end component; --uart
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component eth_dma
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port(clk : in std_logic; --25 MHz
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reset : in std_logic;
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enable_eth : in std_logic;
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select_eth : in std_logic;
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rec_isr : out std_logic;
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send_isr : out std_logic;
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address : out std_logic_vector(31 downto 2); --to DDR
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byte_we : out std_logic_vector(3 downto 0);
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data_write : out std_logic_vector(31 downto 0);
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data_read : in std_logic_vector(31 downto 0);
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pause_in : in std_logic;
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mem_address : in std_logic_vector(31 downto 2); --from CPU
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mem_byte_we : in std_logic_vector(3 downto 0);
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data_w : in std_logic_vector(31 downto 0);
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pause_out : out std_logic;
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E_RX_CLK : in std_logic; --2.5 MHz receive
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E_RX_DV : in std_logic; --data valid
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E_RXD : in std_logic_vector(3 downto 0); --receive nibble
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E_TX_CLK : in std_logic; --2.5 MHz transmit
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E_TX_EN : out std_logic; --transmit enable
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E_TXD : out std_logic_vector(3 downto 0)); --transmit nibble
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end component; --eth_dma
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component plasma
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generic(memory_type : string := "XILINX_X16"; --"DUAL_PORT_" "ALTERA_LPM";
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log_file : string := "UNUSED");
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port(clk_in : in std_logic;
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rst_in : in std_logic;
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uart_write : out std_logic;
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uart_read : in std_logic;
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addr : in std_logic_vector(12 downto 0);
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sram_data : in std_logic_vector(7 downto 0);
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nwe : in std_logic;
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noe : in std_logic;
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ncs : in std_logic;
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irq_pin : out std_logic;
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led : out std_logic);
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end component; --plasma
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component ddr_ctrl
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port(clk : in std_logic;
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clk_2x : in std_logic;
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reset_in : in std_logic;
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address : in std_logic_vector(25 downto 2);
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byte_we : in std_logic_vector(3 downto 0);
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data_w : in std_logic_vector(31 downto 0);
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data_r : out std_logic_vector(31 downto 0);
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active : in std_logic;
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no_start : in std_logic;
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no_stop : in std_logic;
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pause : out std_logic;
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SD_CK_P : out std_logic; --clock_positive
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|
SD_CK_N : out std_logic; --clock_negative
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SD_CKE : out std_logic; --clock_enable
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SD_BA : out std_logic_vector(1 downto 0); --bank_address
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SD_A : out std_logic_vector(12 downto 0); --address(row or col)
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SD_CS : out std_logic; --chip_select
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SD_RAS : out std_logic; --row_address_strobe
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SD_CAS : out std_logic; --column_address_strobe
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SD_WE : out std_logic; --write_enable
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SD_DQ : inout std_logic_vector(15 downto 0); --data
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SD_UDM : out std_logic; --upper_byte_enable
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|
SD_UDQS : inout std_logic; --upper_data_strobe
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SD_LDM : out std_logic; --low_byte_enable
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SD_LDQS : inout std_logic); --low_data_strobe
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end component; --ddr
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end; --package mlite_pack
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package body mlite_pack is
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function bv_adder(a : in std_logic_vector;
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b : in std_logic_vector;
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do_add: in std_logic) return std_logic_vector is
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variable carry_in : std_logic;
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|
variable bb : std_logic_vector(a'length-1 downto 0);
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variable result : std_logic_vector(a'length downto 0);
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|
begin
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if do_add = '1' then
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bb := b;
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carry_in := '0';
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|
else
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|
bb := not b;
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|
carry_in := '1';
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end if;
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for index in 0 to a'length-1 loop
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result(index) := a(index) xor bb(index) xor carry_in;
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carry_in := (carry_in and (a(index) or bb(index))) or
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|
(a(index) and bb(index));
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end loop;
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|
result(a'length) := carry_in xnor do_add;
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|
return result;
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|
end; --function
|
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|
|
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|
function bv_negate(a : in std_logic_vector) return std_logic_vector is
|
|
variable carry_in : std_logic;
|
|
variable not_a : std_logic_vector(a'length-1 downto 0);
|
|
variable result : std_logic_vector(a'length-1 downto 0);
|
|
begin
|
|
not_a := not a;
|
|
carry_in := '1';
|
|
for index in a'reverse_range loop
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|
result(index) := not_a(index) xor carry_in;
|
|
carry_in := carry_in and not_a(index);
|
|
end loop;
|
|
return result;
|
|
end; --function
|
|
|
|
|
|
function bv_increment(a : in std_logic_vector(31 downto 2)
|
|
) return std_logic_vector is
|
|
variable carry_in : std_logic;
|
|
variable result : std_logic_vector(31 downto 2);
|
|
begin
|
|
carry_in := '1';
|
|
for index in 2 to 31 loop
|
|
result(index) := a(index) xor carry_in;
|
|
carry_in := a(index) and carry_in;
|
|
end loop;
|
|
return result;
|
|
end; --function
|
|
|
|
|
|
function bv_inc(a : in std_logic_vector
|
|
) return std_logic_vector is
|
|
variable carry_in : std_logic;
|
|
variable result : std_logic_vector(a'length-1 downto 0);
|
|
begin
|
|
carry_in := '1';
|
|
for index in 0 to a'length-1 loop
|
|
result(index) := a(index) xor carry_in;
|
|
carry_in := a(index) and carry_in;
|
|
end loop;
|
|
return result;
|
|
end; --function
|
|
|
|
end; --package body
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