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34 lines
680 B
Verilog
Executable File
34 lines
680 B
Verilog
Executable File
`timescale 1ns / 1ps
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module writePulseGenerator (input clk,
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input snwe,
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input sncs,
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input reset,
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output reg we);
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reg w_st;
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// write access cpu to bram
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always @(posedge clk)
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if(~reset) {w_st, we} <= 0;
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else begin
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case (w_st)
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0: begin
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we <= 0;
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if(sncs | snwe)
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w_st <= 1;
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end
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1: begin
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if(~(sncs | snwe))
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begin
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we <= 1;
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w_st <= 0;
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end
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else we <= 0;
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end
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endcase
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end
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endmodule
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