2009-05-06 21:12:49 +03:00
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This is an incomplete proof of concept that I applied to be able to
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build a 64 bit kernel with GCC-4.4. It doesn't handle the 32 bit case
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or the R4000_WAR case.
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Comments welcome.
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Signed-off-by: David Daney <ddaney@caviumnetworks.com>
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---
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arch/mips/include/asm/compiler.h | 7 +++++++
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arch/mips/include/asm/delay.h | 4 ++++
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2 files changed, 11 insertions(+), 0 deletions(-)
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--- a/arch/mips/include/asm/compiler.h
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+++ b/arch/mips/include/asm/compiler.h
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2009-06-03 16:42:28 +03:00
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@@ -26,4 +26,11 @@ typedef u64 uintx_t;
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#endif
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2009-05-06 21:12:49 +03:00
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#endif
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+#if __GNUC__ > 4 || (__GNUC__ == 4 && __GNUC_MINOR__ >= 4)
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+#define GCC_NO_H_CONSTRAINT
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+#ifdef CONFIG_64BIT
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+typedef unsigned int uint128_t __attribute__((mode(TI)));
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+#endif
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+#endif
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+
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#endif /* _ASM_COMPILER_H */
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--- a/arch/mips/include/asm/delay.h
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+++ b/arch/mips/include/asm/delay.h
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2009-06-03 16:42:28 +03:00
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@@ -67,10 +67,14 @@ static inline unsigned long __usecs_to_l
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2009-05-06 21:12:49 +03:00
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: "r" (usecs), "r" (lpj)
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: GCC_REG_ACCUM);
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else if (sizeof(long) == 8 && !R4000_WAR)
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+#ifdef GCC_NO_H_CONSTRAINT
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+ usecs = ((uint128_t)usecs * lpj) >> 64;
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+#else
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__asm__("dmultu\t%2, %3"
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: "=h" (usecs), "=l" (lo)
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: "r" (usecs), "r" (lpj)
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: GCC_REG_ACCUM);
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+#endif
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else if (sizeof(long) == 8 && R4000_WAR)
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__asm__("dmultu\t%3, %4\n\tmfhi\t%0"
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: "=r" (usecs), "=h" (hi), "=l" (lo)
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