mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
synced 2024-11-18 05:24:03 +02:00
[adm5120] more USB driver fixes [http://openwrt.pastebin.ca/768610 bootlog :)]
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@9530 3c298f89-4303-0410-b956-a3cf2f4a3e73
This commit is contained in:
juhosg
parent
8c23d0644a
commit
00549f6de0
@ -243,7 +243,7 @@ admhc_dump_roothub(
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{
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u32 temp, i;
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temp = admhc_get_rhdesc(ahcd);
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temp = admhc_read_rhdesc(ahcd);
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if (temp == ~(u32)0)
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return;
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@ -267,7 +267,7 @@ admhc_dump_roothub(
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}
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for (i = 0; i < ahcd->num_ports; i++) {
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temp = admhc_get_portstatus(ahcd, i);
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temp = admhc_read_portstatus(ahcd, i);
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dbg_port_sw(ahcd, i, temp, next, size);
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}
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}
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@ -22,7 +22,7 @@
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#include <linux/signal.h>
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#include <asm/bootinfo.h>
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#include <asm/mach-adm5120/adm5120_defs.h>
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#include <adm5120_defs.h>
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#ifdef DEBUG
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#define HCD_DBG(f, a...) printk(KERN_DEBUG "%s: " f, hcd_name, ## a)
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@ -45,13 +45,14 @@
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#include "../core/hcd.h"
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#include "../core/hub.h"
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#define DRIVER_VERSION "v0.03"
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#define DRIVER_VERSION "v0.04"
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#define DRIVER_AUTHOR "Gabor Juhos <juhosg at openwrt.org>"
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#define DRIVER_DESC "ADMtek USB 1.1 Host Controller Driver"
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/*-------------------------------------------------------------------------*/
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#define ADMHC_VERBOSE_DEBUG /* not always helpful */
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#define ADMHC_POLL_RH
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#undef ADMHC_LOCK_DMA
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/* For initializing controller (mask in an HCFS mode too) */
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@ -349,7 +350,7 @@ static int admhc_get_frame_number(struct usb_hcd *hcd)
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static void admhc_usb_reset(struct admhcd *ahcd)
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{
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ahcd->host_control = ADMHC_BUSS_RESET;
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admhc_writel(ahcd, ahcd->host_control ,&ahcd->regs->host_control);
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admhc_writel(ahcd, ahcd->host_control, &ahcd->regs->host_control);
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}
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/* admhc_shutdown forcibly disables IRQs and DMA, helping kexec and
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@ -466,7 +467,7 @@ static int admhc_init(struct admhcd *ahcd)
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/* Read the number of ports unless overridden */
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if (ahcd->num_ports == 0)
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ahcd->num_ports = admhc_get_rhdesc(ahcd) & ADMHC_RH_NUMP;
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ahcd->num_ports = admhc_read_rhdesc(ahcd) & ADMHC_RH_NUMP;
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ret = admhc_mem_init(ahcd);
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if (ret)
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@ -531,18 +532,16 @@ static int admhc_run(struct admhcd *ahcd)
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admhc_writel(ahcd, ahcd->host_control, &ahcd->regs->host_control);
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msleep(temp);
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temp = admhc_get_rhdesc(ahcd);
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temp = admhc_read_rhdesc(ahcd);
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if (!(temp & ADMHC_RH_NPS)) {
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/* power down each port */
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for (temp = 0; temp < ahcd->num_ports; temp++)
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admhc_writel(ahcd, ADMHC_PS_CPP,
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&ahcd->regs->portstatus[temp]);
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admhc_write_portstatus(ahcd, temp, ADMHC_PS_CPP);
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}
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/* 2msec timelimit here means no irqs/preempt */
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spin_lock_irq(&ahcd->lock);
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retry:
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admhc_writel(ahcd, ADMHC_CTRL_SR, &ahcd->regs->gencontrol);
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temp = 30; /* ... allow extra time */
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while ((admhc_readl(ahcd, &ahcd->regs->gencontrol) & ADMHC_CTRL_SR) != 0) {
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@ -615,25 +614,23 @@ static irqreturn_t admhc_irq(struct usb_hcd *hcd)
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u32 ints;
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ints = admhc_readl(ahcd, ®s->int_status);
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if ((ints & ADMHC_INTR_INTA) == 0) {
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if (!(ints & ADMHC_INTR_INTA))
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/* no unmasked interrupt status is set */
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return IRQ_NONE;
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}
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ints &= admhc_readl(ahcd, ®s->int_enable);
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if (!ints)
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return IRQ_NONE;
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if (ints & ADMHC_INTR_FATI) {
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/* e.g. due to PCI Master/Target Abort */
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admhc_disable(ahcd);
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admhc_err(ahcd, "Fatal Error, controller disabled\n");
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admhc_dump(ahcd, 1);
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admhc_usb_reset(ahcd);
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}
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if (ints & ADMHC_INTR_BABI) {
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admhc_intr_disable(ahcd, ADMHC_INTR_MIE);
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admhc_err(ahcd, "Babble Detected\n");
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admhc_disable(ahcd);
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admhc_err(ahcd, "Babble Detected\n");
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admhc_usb_reset(ahcd);
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}
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@ -711,7 +708,7 @@ static void admhc_stop(struct usb_hcd *hcd)
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flush_scheduled_work();
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admhc_usb_reset(ahcd);
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admhc_intr_disable(ahcd, ADMHC_INTR_MIE);
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admhc_intr_disable(ahcd, ~0);
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free_irq(hcd->irq, hcd);
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hcd->irq = -1;
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@ -17,42 +17,42 @@
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admhc_dbg(hc, \
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"%s port%d " \
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"= 0x%08x%s%s%s%s%s%s%s%s%s%s%s%s\n", \
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label, num, temp, \
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(temp & ADMHC_PS_PRSC) ? " PRSC" : "", \
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(temp & ADMHC_PS_OCIC) ? " OCIC" : "", \
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(temp & ADMHC_PS_PSSC) ? " PSSC" : "", \
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(temp & ADMHC_PS_PESC) ? " PESC" : "", \
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(temp & ADMHC_PS_CSC) ? " CSC" : "", \
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label, num, value, \
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(value & ADMHC_PS_PRSC) ? " PRSC" : "", \
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(value & ADMHC_PS_OCIC) ? " OCIC" : "", \
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(value & ADMHC_PS_PSSC) ? " PSSC" : "", \
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(value & ADMHC_PS_PESC) ? " PESC" : "", \
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(value & ADMHC_PS_CSC) ? " CSC" : "", \
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\
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(temp & ADMHC_PS_LSDA) ? " LSDA" : "", \
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(temp & ADMHC_PS_PPS) ? " PPS" : "", \
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(temp & ADMHC_PS_PRS) ? " PRS" : "", \
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(temp & ADMHC_PS_POCI) ? " POCI" : "", \
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(temp & ADMHC_PS_PSS) ? " PSS" : "", \
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(value & ADMHC_PS_LSDA) ? " LSDA" : "", \
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(value & ADMHC_PS_PPS) ? " PPS" : "", \
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(value & ADMHC_PS_PRS) ? " PRS" : "", \
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(value & ADMHC_PS_POCI) ? " POCI" : "", \
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(value & ADMHC_PS_PSS) ? " PSS" : "", \
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\
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(temp & ADMHC_PS_PES) ? " PES" : "", \
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(temp & ADMHC_PS_CCS) ? " CCS" : "" \
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(value & ADMHC_PS_PES) ? " PES" : "", \
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(value & ADMHC_PS_CCS) ? " CCS" : "" \
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);
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#define dbg_port_write(hc,label,num,value) \
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admhc_dbg(hc, \
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"%s port%d " \
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"= 0x%08x%s%s%s%s%s%s%s%s%s%s%s%s\n", \
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label, num, temp, \
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(temp & ADMHC_PS_PRSC) ? " PRSC" : "", \
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(temp & ADMHC_PS_OCIC) ? " OCIC" : "", \
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(temp & ADMHC_PS_PSSC) ? " PSSC" : "", \
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(temp & ADMHC_PS_PESC) ? " PESC" : "", \
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(temp & ADMHC_PS_CSC) ? " CSC" : "", \
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label, num, value, \
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(value & ADMHC_PS_PRSC) ? " PRSC" : "", \
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(value & ADMHC_PS_OCIC) ? " OCIC" : "", \
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(value & ADMHC_PS_PSSC) ? " PSSC" : "", \
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(value & ADMHC_PS_PESC) ? " PESC" : "", \
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(value & ADMHC_PS_CSC) ? " CSC" : "", \
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\
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(temp & ADMHC_PS_CPP) ? " CPP" : "", \
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(temp & ADMHC_PS_SPP) ? " SPP" : "", \
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(temp & ADMHC_PS_SPR) ? " SPR" : "", \
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(temp & ADMHC_PS_CPS) ? " CPS" : "", \
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(temp & ADMHC_PS_SPS) ? " SPS" : "", \
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(value & ADMHC_PS_CPP) ? " CPP" : "", \
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(value & ADMHC_PS_SPP) ? " SPP" : "", \
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(value & ADMHC_PS_SPR) ? " SPR" : "", \
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(value & ADMHC_PS_CPS) ? " CPS" : "", \
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(value & ADMHC_PS_SPS) ? " SPS" : "", \
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\
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(temp & ADMHC_PS_SPE) ? " SPE" : "", \
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(temp & ADMHC_PS_CPE) ? " CPE" : "" \
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(value & ADMHC_PS_SPE) ? " SPE" : "", \
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(value & ADMHC_PS_CPE) ? " CPE" : "" \
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);
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/*-------------------------------------------------------------------------*/
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@ -87,7 +87,7 @@ admhc_hub_status_data(struct usb_hcd *hcd, char *buf)
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goto done;
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/* init status */
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status = admhc_get_rhdesc(ahcd);
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status = admhc_read_rhdesc(ahcd);
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if (status & (ADMHC_RH_LPSC | ADMHC_RH_OCIC))
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buf [0] = changed = 1;
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else
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@ -99,7 +99,7 @@ admhc_hub_status_data(struct usb_hcd *hcd, char *buf)
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/* look at each port */
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for (i = 0; i < ahcd->num_ports; i++) {
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status = admhc_get_portstatus(ahcd, i);
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status = admhc_read_portstatus(ahcd, i);
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/* can't autostop if ports are connected */
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any_connected |= (status & ADMHC_PS_CCS);
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@ -125,15 +125,15 @@ done:
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/*-------------------------------------------------------------------------*/
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static void admhc_hub_descriptor(struct admhcd *ahcd,
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struct usb_hub_descriptor *desc)
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static int admhc_get_hub_descriptor(struct admhcd *ahcd, char *buf)
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{
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u32 rh = admhc_get_rhdesc(ahcd);
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u16 temp;
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struct usb_hub_descriptor *desc = (struct usb_hub_descriptor *)buf;
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u32 rh = admhc_read_rhdesc(ahcd);
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u16 temp;
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desc->bDescriptorType = USB_DT_HUB; /* Hub-descriptor */
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desc->bPwrOn2PwrGood = ADMHC_POTPGT/2; /* use default value */
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desc->bHubContrCurrent = 0x00; /* 0mA */
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desc->bHubContrCurrent = 0x00; /* 0mA */
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desc->bNbrPorts = ahcd->num_ports;
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temp = 1 + (ahcd->num_ports / 8);
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@ -152,8 +152,58 @@ static void admhc_hub_descriptor(struct admhcd *ahcd,
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desc->wHubCharacteristics = (__force __u16)cpu_to_hc16(ahcd, temp);
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/* two bitmaps: ports removable, and usb 1.0 legacy PortPwrCtrlMask */
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desc->bitmap [0] = 0;
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desc->bitmap [0] = ~0;
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desc->bitmap[0] = 0;
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desc->bitmap[0] = ~0;
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return 0;
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}
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static int admhc_get_hub_status(struct admhcd *ahcd, char *buf)
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{
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struct usb_hub_status *hs = (struct usb_hub_status *)buf;
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u32 t = admhc_read_rhdesc(ahcd);
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u16 status, change;
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status = 0;
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status |= (t & ADMHC_RH_LPS) ? HUB_STATUS_LOCAL_POWER : 0;
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status |= (t & ADMHC_RH_OCI) ? HUB_STATUS_OVERCURRENT : 0;
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change = 0;
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change |= (t & ADMHC_RH_LPSC) ? HUB_CHANGE_LOCAL_POWER : 0;
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change |= (t & ADMHC_RH_OCIC) ? HUB_CHANGE_OVERCURRENT : 0;
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hs->wHubStatus = (__force __u16)cpu_to_hc16(ahcd, status);
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hs->wHubChange = (__force __u16)cpu_to_hc16(ahcd, change);
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return 0;
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}
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static int admhc_get_port_status(struct admhcd *ahcd, unsigned port, char *buf)
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{
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struct usb_port_status *ps = (struct usb_port_status *)buf;
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u32 t = admhc_read_portstatus(ahcd, port);
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u16 status, change;
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status = 0;
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status |= (t & ADMHC_PS_CCS) ? USB_PORT_STAT_CONNECTION : 0;
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status |= (t & ADMHC_PS_PES) ? USB_PORT_STAT_ENABLE : 0;
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status |= (t & ADMHC_PS_PSS) ? USB_PORT_STAT_SUSPEND : 0;
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status |= (t & ADMHC_PS_POCI) ? USB_PORT_STAT_OVERCURRENT : 0;
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status |= (t & ADMHC_PS_PRS) ? USB_PORT_STAT_RESET : 0;
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status |= (t & ADMHC_PS_PPS) ? USB_PORT_STAT_POWER : 0;
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status |= (t & ADMHC_PS_LSDA) ? USB_PORT_STAT_LOW_SPEED : 0;
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change = 0;
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change |= (t & ADMHC_PS_CSC) ? USB_PORT_STAT_C_CONNECTION : 0;
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change |= (t & ADMHC_PS_PESC) ? USB_PORT_STAT_C_ENABLE : 0;
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change |= (t & ADMHC_PS_PSSC) ? USB_PORT_STAT_C_SUSPEND : 0;
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change |= (t & ADMHC_PS_OCIC) ? USB_PORT_STAT_C_OVERCURRENT : 0;
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change |= (t & ADMHC_PS_PRSC) ? USB_PORT_STAT_C_RESET : 0;
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ps->wPortStatus = (__force __u16)cpu_to_hc16(ahcd, status);
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ps->wPortChange = (__force __u16)cpu_to_hc16(ahcd, change);
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return 0;
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}
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/*-------------------------------------------------------------------------*/
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@ -170,12 +220,12 @@ static int admhc_start_port_reset(struct usb_hcd *hcd, unsigned port)
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port--;
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/* start port reset before HNP protocol times out */
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status = admhc_readl(ahcd, &ahcd->regs->portstatus[port]);
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status = admhc_read_portstatus(ahcd, port);
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if (!(status & ADMHC_PS_CCS))
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return -ENODEV;
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/* khubd will finish the reset later */
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admhc_writel(ahcd, ADMHC_PS_PRS, &ahcd->regs->portstatus[port]);
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admhc_write_portstatus(ahcd, port, ADMHC_PS_PRS);
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return 0;
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}
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@ -208,91 +258,107 @@ static void start_hnp(struct admhcd *ahcd);
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#define tick_before(t1,t2) ((s16)(((s16)(t1))-((s16)(t2))) < 0)
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/* called from some task, normally khubd */
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static inline int root_port_reset(struct admhcd *ahcd, unsigned port)
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static inline int admhc_port_reset(struct admhcd *ahcd, unsigned port)
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{
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#if 0
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/* FIXME: revert to this when frame numbers are updated */
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__hc32 __iomem *portstat = &ahcd->regs->portstatus[port];
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u32 temp;
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u16 now = admhc_readl(ahcd, &ahcd->regs->fmnumber);
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u16 reset_done = now + PORT_RESET_MSEC;
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u32 t;
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int c;
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/* build a "continuous enough" reset signal, with up to
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* 3msec gap between pulses. scheduler HZ==100 must work;
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* this might need to be deadline-scheduled.
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*/
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admhc_vdbg(ahcd, "reset port%d\n", port);
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t = admhc_read_portstatus(ahcd, port);
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if (!(t & ADMHC_PS_CCS))
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return -ENODEV;
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if ((t & ADMHC_PS_PRS))
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return 0;
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admhc_write_portstatus(ahcd, port, ADMHC_PS_PRS);
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c = 0;
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do {
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/* spin until any current reset finishes */
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for (;;) {
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temp = admhc_readl(ahcd, portstat);
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/* handle e.g. CardBus eject */
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if (temp == ~(u32)0)
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return -ESHUTDOWN;
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if (!(temp & ADMHC_PS_PRS))
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break;
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udelay (500);
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}
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if (!(temp & ADMHC_PS_CCS))
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break;
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if (temp & ADMHC_PS_PRSC)
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admhc_writel(ahcd, ADMHC_PS_PRSC, portstat);
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/* start the next reset, sleep till it's probably done */
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admhc_writel(ahcd, ADMHC_PS_PRS, portstat);
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msleep(PORT_RESET_HW_MSEC);
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now = admhc_readl(ahcd, &ahcd->regs->fmnumber);
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} while (tick_before(now, reset_done));
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/* caller synchronizes using PRSC */
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#else
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__hc32 __iomem *portstat = &ahcd->regs->portstatus[port];
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u32 temp;
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unsigned long reset_done = jiffies + msecs_to_jiffies(PORT_RESET_MSEC);
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/* build a "continuous enough" reset signal, with up to
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* 3msec gap between pulses. scheduler HZ==100 must work;
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* this might need to be deadline-scheduled.
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*/
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do {
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/* spin until any current reset finishes */
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for (;;) {
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temp = admhc_readl(ahcd, portstat);
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/* handle e.g. CardBus eject */
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if (temp == ~(u32)0)
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return -ESHUTDOWN;
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if (!(temp & ADMHC_PS_PRS))
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break;
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udelay (500);
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}
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if (!(temp & ADMHC_PS_CCS))
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t = admhc_read_portstatus(ahcd, port);
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if (t & ADMHC_PS_PRSC)
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break;
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if (temp & ADMHC_PS_PRSC)
|
||||
admhc_writel(ahcd, ADMHC_PS_PRSC, portstat);
|
||||
if (++c > 20) {
|
||||
admhc_err(ahcd, "port%d reset timed out\n",port);
|
||||
return -EPIPE;
|
||||
}
|
||||
|
||||
/* start the next reset, sleep till it's probably done */
|
||||
admhc_writel(ahcd, ADMHC_PS_PRS, portstat);
|
||||
msleep(PORT_RESET_HW_MSEC);
|
||||
} while (time_before(jiffies, reset_done));
|
||||
mdelay(PORT_RESET_HW_MSEC);
|
||||
} while (1);
|
||||
admhc_vdbg(ahcd, "port%d reset completed within %dms\n", port,
|
||||
c * PORT_RESET_HW_MSEC);
|
||||
|
||||
t = admhc_read_portstatus(ahcd, port);
|
||||
if (!(t & ADMHC_PS_CCS)) {
|
||||
admhc_err(ahcd, "port%d is not connected after reset\n",port);
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
admhc_write_portstatus(ahcd, port, ADMHC_PS_SPE);
|
||||
c = 0;
|
||||
do {
|
||||
t = admhc_read_portstatus(ahcd, port);
|
||||
if (t & ADMHC_PS_PESC)
|
||||
break;
|
||||
|
||||
if (++c > 20) {
|
||||
admhc_err(ahcd, "port%d enable timed out\n",port);
|
||||
return -EPIPE;
|
||||
}
|
||||
|
||||
mdelay(PORT_RESET_HW_MSEC);
|
||||
} while (1);
|
||||
admhc_vdbg(ahcd, "port%d enable completed within %dms\n", port,
|
||||
c * PORT_RESET_HW_MSEC);
|
||||
|
||||
admhc_write_portstatus(ahcd, port, ADMHC_PS_CSC);
|
||||
|
||||
admhc_writel(ahcd, ADMHC_PS_SPE | ADMHC_PS_CSC, portstat);
|
||||
msleep(100);
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int admhc_hub_control (
|
||||
struct usb_hcd *hcd,
|
||||
u16 typeReq,
|
||||
u16 wValue,
|
||||
u16 wIndex,
|
||||
char *buf,
|
||||
u16 wLength
|
||||
) {
|
||||
static inline int admhc_port_enable(struct admhcd *ahcd, unsigned port)
|
||||
{
|
||||
u32 t;
|
||||
|
||||
admhc_vdbg(ahcd, "enable port%d\n", port);
|
||||
t = admhc_read_portstatus(ahcd, port);
|
||||
if (!(t & ADMHC_PS_CCS))
|
||||
return -ENODEV;
|
||||
|
||||
admhc_write_portstatus(ahcd, port, ADMHC_PS_SPE);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline int admhc_port_disable(struct admhcd *ahcd, unsigned port)
|
||||
{
|
||||
u32 t;
|
||||
|
||||
admhc_vdbg(ahcd, "disable port%d\n", port);
|
||||
t = admhc_read_portstatus(ahcd, port);
|
||||
if (!(t & ADMHC_PS_CCS))
|
||||
return -ENODEV;
|
||||
|
||||
admhc_write_portstatus(ahcd, ADMHC_PS_CPE, port);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline int admhc_port_write(struct admhcd *ahcd, unsigned port,
|
||||
u32 val)
|
||||
{
|
||||
dbg_port_write(ahcd, "write", port, val);
|
||||
admhc_write_portstatus(ahcd, port, val);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int admhc_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
|
||||
u16 wIndex, char *buf, u16 wLength)
|
||||
{
|
||||
struct admhcd *ahcd = hcd_to_admhcd(hcd);
|
||||
int ports = hcd_to_bus (hcd)->root_hub->maxchild;
|
||||
u32 temp;
|
||||
int ports = hcd_to_bus(hcd)->root_hub->maxchild;
|
||||
int ret = 0;
|
||||
|
||||
if (unlikely(!test_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags)))
|
||||
@ -319,55 +385,50 @@ static int admhc_hub_control (
|
||||
|
||||
switch (wValue) {
|
||||
case USB_PORT_FEAT_ENABLE:
|
||||
temp = ADMHC_PS_CPE;
|
||||
ret = admhc_port_disable(ahcd, wIndex);
|
||||
break;
|
||||
case USB_PORT_FEAT_SUSPEND:
|
||||
temp = ADMHC_PS_CPS;
|
||||
ret = admhc_port_write(ahcd, wIndex, ADMHC_PS_CPS);
|
||||
break;
|
||||
case USB_PORT_FEAT_POWER:
|
||||
temp = ADMHC_PS_CPP;
|
||||
ret = admhc_port_write(ahcd, wIndex, ADMHC_PS_CPP);
|
||||
break;
|
||||
case USB_PORT_FEAT_C_CONNECTION:
|
||||
temp = ADMHC_PS_CSC;
|
||||
ret = admhc_port_write(ahcd, wIndex, ADMHC_PS_CSC);
|
||||
break;
|
||||
case USB_PORT_FEAT_C_ENABLE:
|
||||
temp = ADMHC_PS_PESC;
|
||||
ret = admhc_port_write(ahcd, wIndex, ADMHC_PS_PESC);
|
||||
break;
|
||||
case USB_PORT_FEAT_C_SUSPEND:
|
||||
temp = ADMHC_PS_PSSC;
|
||||
ret = admhc_port_write(ahcd, wIndex, ADMHC_PS_PSSC);
|
||||
break;
|
||||
case USB_PORT_FEAT_C_OVER_CURRENT:
|
||||
temp = ADMHC_PS_OCIC;
|
||||
ret = admhc_port_write(ahcd, wIndex, ADMHC_PS_OCIC);
|
||||
break;
|
||||
case USB_PORT_FEAT_C_RESET:
|
||||
temp = ADMHC_PS_PRSC;
|
||||
ret = admhc_port_write(ahcd, wIndex, ADMHC_PS_PRSC);
|
||||
break;
|
||||
default:
|
||||
goto error;
|
||||
}
|
||||
admhc_writel(ahcd, temp, &ahcd->regs->portstatus[wIndex]);
|
||||
break;
|
||||
case GetHubDescriptor:
|
||||
admhc_hub_descriptor(ahcd, (struct usb_hub_descriptor *) buf);
|
||||
ret = admhc_get_hub_descriptor(ahcd, buf);
|
||||
break;
|
||||
case GetHubStatus:
|
||||
temp = admhc_get_rhdesc(ahcd);
|
||||
temp &= ~(ADMHC_RH_CRWE | ADMHC_RH_DRWE);
|
||||
put_unaligned(cpu_to_le32 (temp), (__le32 *) buf);
|
||||
ret = admhc_get_hub_status(ahcd, buf);
|
||||
break;
|
||||
case GetPortStatus:
|
||||
if (!wIndex || wIndex > ports)
|
||||
goto error;
|
||||
wIndex--;
|
||||
temp = admhc_get_portstatus(ahcd, wIndex);
|
||||
put_unaligned(cpu_to_le32 (temp), (__le32 *) buf);
|
||||
|
||||
dbg_port(ahcd, "GetPortStatus", wIndex, temp);
|
||||
ret = admhc_get_port_status(ahcd, wIndex, buf);
|
||||
break;
|
||||
case SetHubFeature:
|
||||
switch (wValue) {
|
||||
case C_HUB_OVER_CURRENT:
|
||||
// FIXME: this can be cleared, yes?
|
||||
/* FIXME: this can be cleared, yes? */
|
||||
case C_HUB_LOCAL_POWER:
|
||||
break;
|
||||
default:
|
||||
@ -381,8 +442,10 @@ static int admhc_hub_control (
|
||||
|
||||
switch (wValue) {
|
||||
case USB_PORT_FEAT_ENABLE:
|
||||
admhc_writel(ahcd, ADMHC_PS_SPE,
|
||||
&ahcd->regs->portstatus[wIndex]);
|
||||
ret = admhc_port_enable(ahcd, wIndex);
|
||||
break;
|
||||
case USB_PORT_FEAT_RESET:
|
||||
ret = admhc_port_reset(ahcd, wIndex);
|
||||
break;
|
||||
case USB_PORT_FEAT_SUSPEND:
|
||||
#ifdef CONFIG_USB_OTG
|
||||
@ -391,15 +454,10 @@ static int admhc_hub_control (
|
||||
start_hnp(ahcd);
|
||||
else
|
||||
#endif
|
||||
admhc_writel(ahcd, ADMHC_PS_SPS,
|
||||
&ahcd->regs->portstatus[wIndex]);
|
||||
ret = admhc_port_write(ahcd, wIndex, ADMHC_PS_SPS);
|
||||
break;
|
||||
case USB_PORT_FEAT_POWER:
|
||||
admhc_writel(ahcd, ADMHC_PS_SPP,
|
||||
&ahcd->regs->portstatus[wIndex]);
|
||||
break;
|
||||
case USB_PORT_FEAT_RESET:
|
||||
ret = root_port_reset(ahcd, wIndex);
|
||||
ret = admhc_port_write(ahcd, wIndex, ADMHC_PS_SPP);
|
||||
break;
|
||||
default:
|
||||
goto error;
|
||||
@ -411,6 +469,7 @@ error:
|
||||
/* "protocol stall" on error */
|
||||
ret = -EPIPE;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
||||
@ -147,7 +147,7 @@ static struct urb_priv *urb_priv_alloc(struct admhcd *ahcd, int num_tds,
|
||||
if (!priv)
|
||||
goto err;
|
||||
|
||||
/* allocate the TDs (deferring hash chain updates) */
|
||||
/* allocate the TDs */
|
||||
for (i = 0; i < num_tds; i++) {
|
||||
priv->td[i] = td_alloc(ahcd, mem_flags);
|
||||
if (priv->td[i] == NULL)
|
||||
|
||||
@ -436,8 +436,13 @@ static inline struct usb_hcd *admhcd_to_hcd(const struct admhcd *ahcd)
|
||||
#define STUB_DEBUG_FILES
|
||||
#endif /* DEBUG */
|
||||
|
||||
#define admhc_dbg(ahcd, fmt, args...) \
|
||||
printk(KERN_DEBUG "adm5120-hcd: " fmt , ## args )
|
||||
#ifdef DEBUG
|
||||
# define admhc_dbg(ahcd, fmt, args...) \
|
||||
printk(KERN_DEBUG "adm5120-hcd: " fmt , ## args )
|
||||
#else
|
||||
# define admhc_dbg(ahcd, fmt, args...) do { } while (0)
|
||||
#endif
|
||||
|
||||
#define admhc_err(ahcd, fmt, args...) \
|
||||
printk(KERN_ERR "adm5120-hcd: " fmt , ## args )
|
||||
#define ahcd_info(ahcd, fmt, args...) \
|
||||
@ -645,16 +650,22 @@ static inline void periodic_reinit(struct admhcd *ahcd)
|
||||
&ahcd->regs->fminterval);
|
||||
}
|
||||
|
||||
static inline u32 admhc_get_rhdesc(struct admhcd *ahcd)
|
||||
static inline u32 admhc_read_rhdesc(struct admhcd *ahcd)
|
||||
{
|
||||
return admhc_readl(ahcd, &ahcd->regs->rhdesc);
|
||||
}
|
||||
|
||||
static inline u32 admhc_get_portstatus(struct admhcd *ahcd, int port)
|
||||
static inline u32 admhc_read_portstatus(struct admhcd *ahcd, int port)
|
||||
{
|
||||
return admhc_readl(ahcd, &ahcd->regs->portstatus[port]);
|
||||
}
|
||||
|
||||
static inline void admhc_write_portstatus(struct admhcd *ahcd, int port,
|
||||
u32 value)
|
||||
{
|
||||
admhc_writel(ahcd, value, &ahcd->regs->portstatus[port]);
|
||||
}
|
||||
|
||||
static inline void roothub_write_status(struct admhcd *ahcd, u32 value)
|
||||
{
|
||||
/* FIXME: read-only bits must be masked out */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user