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git://projects.qi-hardware.com/openwrt-xburst.git
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USB iso mode fixes
Resolves an issue where isochronouse USB would cause the driver to hang as well as scheduling issues. Signed-off-by: Tim Harvey <tharvey@gateworks.com> git-svn-id: svn://svn.openwrt.org/openwrt/trunk@33579 3c298f89-4303-0410-b956-a3cf2f4a3e73
This commit is contained in:
parent
98353f24a2
commit
07511ec793
@ -7887,7 +7887,7 @@
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+#endif
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--- /dev/null
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+++ b/drivers/usb/dwc/otg_hcd.c
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@@ -0,0 +1,2735 @@
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@@ -0,0 +1,2752 @@
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+/* ==========================================================================
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+ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd.c $
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+ * $Revision: #75 $
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@ -8056,7 +8056,9 @@
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+ dwc_otg_qh_t *qh;
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+ struct list_head *qtd_item;
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+ dwc_otg_qtd_t *qtd;
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+ unsigned long flags;
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+
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+ SPIN_LOCK_IRQSAVE(&hcd->lock, flags);
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+ list_for_each(qh_item, qh_list) {
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+ qh = list_entry(qh_item, dwc_otg_qh_t, qh_list_entry);
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+ for (qtd_item = qh->qtd_list.next;
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@ -8070,6 +8072,7 @@
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+ dwc_otg_hcd_qtd_remove_and_free(hcd, qtd);
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+ }
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+ }
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+ SPIN_UNLOCK_IRQRESTORE(&hcd->lock, flags);
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+}
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+
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+/**
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@ -8313,10 +8316,14 @@
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+ hcd->regs = otg_dev->base;
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+ hcd->self.otg_port = 1;
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+
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+ /* Integrate TT in root hub, by default this is disbled. */
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+ hcd->has_tt = 1;
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+
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+ /* Initialize the DWC OTG HCD. */
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+ dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
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+ dwc_otg_hcd->core_if = otg_dev->core_if;
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+ otg_dev->hcd = dwc_otg_hcd;
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+ init_hcd_usecs(dwc_otg_hcd);
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+
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+ /* */
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+ spin_lock_init(&dwc_otg_hcd->lock);
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@ -8534,6 +8541,7 @@
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+{
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+ struct list_head *item;
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+ dwc_otg_qh_t *qh;
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+ unsigned long flags;
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+
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+ if (!qh_list->next) {
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+ /* The list hasn't been initialized yet. */
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@ -8543,10 +8551,12 @@
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+ /* Ensure there are no QTDs or URBs left. */
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+ kill_urbs_in_qh_list(hcd, qh_list);
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+
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+ SPIN_LOCK_IRQSAVE(&hcd->lock, flags);
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+ for (item = qh_list->next; item != qh_list; item = qh_list->next) {
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+ qh = list_entry(item, dwc_otg_qh_t, qh_list_entry);
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+ dwc_otg_hcd_qh_remove_and_free(hcd, qh);
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+ }
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+ SPIN_UNLOCK_IRQRESTORE(&hcd->lock, flags);
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+}
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+
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+/**
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@ -8838,6 +8848,10 @@
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+ urb_qtd = (dwc_otg_qtd_t *)urb->hcpriv;
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+ qh = (dwc_otg_qh_t *)ep->hcpriv;
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+
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+ if (urb_qtd == NULL) {
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+ SPIN_UNLOCK_IRQRESTORE(&dwc_otg_hcd->lock, flags);
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+ return 0;
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+ }
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+#ifdef DEBUG
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+ if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) {
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+ dump_urb_info(urb, "dwc_otg_hcd_urb_dequeue");
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@ -8869,15 +8883,17 @@
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+ */
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+ dwc_otg_hcd_qtd_remove_and_free(dwc_otg_hcd, urb_qtd);
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+ if (urb_qtd == qh->qtd_in_process) {
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+ /* Note that dwc_otg_hcd_qh_deactivate() locks the spin_lock again */
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+ SPIN_UNLOCK_IRQRESTORE(&dwc_otg_hcd->lock, flags);
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+ dwc_otg_hcd_qh_deactivate(dwc_otg_hcd, qh, 0);
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+ qh->channel = NULL;
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+ qh->qtd_in_process = NULL;
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+ } else if (list_empty(&qh->qtd_list)) {
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+ dwc_otg_hcd_qh_remove(dwc_otg_hcd, qh);
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+ } else {
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+ if (list_empty(&qh->qtd_list))
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+ dwc_otg_hcd_qh_remove(dwc_otg_hcd, qh);
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+ SPIN_UNLOCK_IRQRESTORE(&dwc_otg_hcd->lock, flags);
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+ }
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+
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+ SPIN_UNLOCK_IRQRESTORE(&dwc_otg_hcd->lock, flags);
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+
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+ urb->hcpriv = NULL;
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+
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+ /* Higher layer software sets URB status. */
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@ -8928,7 +8944,6 @@
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+ ep->hcpriv = NULL;
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+done:
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+ SPIN_UNLOCK_IRQRESTORE(&dwc_otg_hcd->lock, flags);
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+
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+}
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+
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+/** Handles host mode interrupts for the DWC_otg controller. Returns IRQ_NONE if
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@ -10085,6 +10100,7 @@
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+ DWC_DEBUGPL(DBG_HCD, " Select Transactions\n");
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+#endif
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+
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+ spin_lock(&hcd->lock);
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+ /* Process entries in the periodic ready list. */
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+ qh_ptr = hcd->periodic_sched_ready.next;
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+ while (qh_ptr != &hcd->periodic_sched_ready &&
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@ -10133,6 +10149,7 @@
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+
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+ hcd->non_periodic_channels++;
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+ }
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+ spin_unlock(&hcd->lock);
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+
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+ return ret_val;
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+}
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@ -10625,7 +10642,7 @@
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+#endif /* DWC_DEVICE_ONLY */
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--- /dev/null
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+++ b/drivers/usb/dwc/otg_hcd.h
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@@ -0,0 +1,647 @@
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@@ -0,0 +1,652 @@
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+/* ==========================================================================
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+ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd.h $
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+ * $Revision: #45 $
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@ -10825,6 +10842,9 @@
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+ /** (micro)frame at which last start split was initialized. */
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+ uint16_t start_split_frame;
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+
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+ u16 speed;
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+ u16 frame_usecs[8];
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+
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+ /** @} */
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+
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+ /** Entry for QH in either the periodic or non-periodic schedule. */
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@ -10928,6 +10948,18 @@
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+ */
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+ uint16_t periodic_usecs;
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+
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+ /*
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+ * Total bandwidth claimed so far for all periodic transfers
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+ * in a frame.
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+ * This will include a mixture of HS and FS transfers.
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+ * Units are microseconds per (micro)frame.
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+ * We have a budget per frame and have to schedule
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+ * transactions accordingly.
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+ * Watch out for the fact that things are actually scheduled for the
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+ * "next frame".
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+ */
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+ u16 frame_usecs[8];
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+
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+ /**
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+ * Frame number read from the core at SOF. The value ranges from 0 to
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+ * DWC_HFNUM_MAX_FRNUM.
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@ -11089,6 +11121,7 @@
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+/** @{ */
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+
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+/* Implemented in dwc_otg_hcd_queue.c */
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+extern int init_hcd_usecs(dwc_otg_hcd_t *hcd);
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+extern dwc_otg_qh_t *dwc_otg_hcd_qh_create(dwc_otg_hcd_t *hcd, struct urb *urb);
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+extern void dwc_otg_hcd_qh_init(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh, struct urb *urb);
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+extern void dwc_otg_hcd_qh_free(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh);
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@ -11130,21 +11163,10 @@
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+ kfree(qtd);
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+}
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+
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+/** Removes a QTD from list.
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+ * @param[in] hcd HCD instance.
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+ * @param[in] qtd QTD to remove from list. */
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+static inline void dwc_otg_hcd_qtd_remove(dwc_otg_hcd_t *hcd, dwc_otg_qtd_t *qtd)
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+{
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+ unsigned long flags;
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+ SPIN_LOCK_IRQSAVE(&hcd->lock, flags);
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+ list_del(&qtd->qtd_list_entry);
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+ SPIN_UNLOCK_IRQRESTORE(&hcd->lock, flags);
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+}
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+
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+/** Remove and free a QTD */
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+static inline void dwc_otg_hcd_qtd_remove_and_free(dwc_otg_hcd_t *hcd, dwc_otg_qtd_t *qtd)
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+{
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+ dwc_otg_hcd_qtd_remove(hcd, qtd);
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+ list_del(&qtd->qtd_list_entry);
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+ dwc_otg_hcd_qtd_free(qtd);
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+}
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+
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@ -11275,7 +11297,7 @@
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+#endif /* DWC_DEVICE_ONLY */
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--- /dev/null
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+++ b/drivers/usb/dwc/otg_hcd_intr.c
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@@ -0,0 +1,1826 @@
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@@ -0,0 +1,1828 @@
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+/* ==========================================================================
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+ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd_intr.c $
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+ * $Revision: #70 $
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@ -11884,6 +11906,7 @@
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+
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+ DWC_DEBUGPL(DBG_HCDV, " %s(%p,%p,%d)\n", __func__, hcd, qh, free_qtd);
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+
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+ spin_lock(&hcd->lock);
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+ qtd = list_entry(qh->qtd_list.next, dwc_otg_qtd_t, qtd_list_entry);
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+
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+ if (qtd->complete_split) {
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@ -11900,6 +11923,7 @@
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+
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+ qh->channel = NULL;
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+ qh->qtd_in_process = NULL;
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+ spin_unlock(&hcd->lock);
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+ dwc_otg_hcd_qh_deactivate(hcd, qh, continue_split);
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+}
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+
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@ -13104,7 +13128,7 @@
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+#endif /* DWC_DEVICE_ONLY */
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--- /dev/null
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+++ b/drivers/usb/dwc/otg_hcd_queue.c
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@@ -0,0 +1,713 @@
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@@ -0,0 +1,794 @@
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+/* ==========================================================================
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+ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd_queue.c $
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+ * $Revision: #33 $
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@ -13262,6 +13286,7 @@
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+ INIT_LIST_HEAD(&qh->qtd_list);
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+ INIT_LIST_HEAD(&qh->qh_list_entry);
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+ qh->channel = NULL;
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+ qh->speed = urb->dev->speed;
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+
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+ /* FS/LS Enpoint on HS Hub
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+ * NOT virtual root hub */
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@ -13283,10 +13308,10 @@
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+
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+ /** @todo Account for split transfers in the bus time. */
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+ int bytecount = dwc_hb_mult(qh->maxp) * dwc_max_packet(qh->maxp);
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+ qh->usecs = usb_calc_bus_time(urb->dev->speed,
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+ qh->usecs = NS_TO_US(usb_calc_bus_time(urb->dev->speed,
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+ usb_pipein(urb->pipe),
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+ (qh->ep_type == USB_ENDPOINT_XFER_ISOC),
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+ bytecount);
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+ bytecount));
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+
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+ /* Start in a slightly future (micro)frame. */
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+ qh->sched_frame = dwc_frame_num_inc(hcd->frame_number,
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@ -13365,73 +13390,159 @@
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+}
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+
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+/**
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+ * Checks that a channel is available for a periodic transfer.
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+ *
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+ * @return 0 if successful, negative error code otherise.
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+ * Microframe scheduler
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+ * track the total use in hcd->frame_usecs
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+ * keep each qh use in qh->frame_usecs
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+ * when surrendering the qh then donate the time back
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+ */
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+static int periodic_channel_available(dwc_otg_hcd_t *hcd)
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+static const u16 max_uframe_usecs[] = { 100, 100, 100, 100, 100, 100, 30, 0 };
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+
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+/*
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+ * called from dwc_otg_hcd.c:dwc_otg_hcd_init
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+ */
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+int init_hcd_usecs(dwc_otg_hcd_t *hcd)
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+{
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+ /*
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+ * Currently assuming that there is a dedicated host channnel for each
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+ * periodic transaction plus at least one host channel for
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+ * non-periodic transactions.
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+ */
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+ int status;
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+ int num_channels;
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+ int i;
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+
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+ num_channels = hcd->core_if->core_params->host_channels;
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+ if ((hcd->periodic_channels + hcd->non_periodic_channels < num_channels) &&
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+ (hcd->periodic_channels < num_channels - 1)) {
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+ status = 0;
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+ }
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+ else {
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+ DWC_NOTICE("%s: Total channels: %d, Periodic: %d, Non-periodic: %d\n",
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+ __func__, num_channels, hcd->periodic_channels,
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+ hcd->non_periodic_channels);
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+ status = -ENOSPC;
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+ }
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+ for (i = 0; i < 8; i++)
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+ hcd->frame_usecs[i] = max_uframe_usecs[i];
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+
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+ return status;
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+ return 0;
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+}
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+
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+/**
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+ * Checks that there is sufficient bandwidth for the specified QH in the
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+ * periodic schedule. For simplicity, this calculation assumes that all the
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+ * transfers in the periodic schedule may occur in the same (micro)frame.
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+ *
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+ * @param hcd The HCD state structure for the DWC OTG controller.
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+ * @param qh QH containing periodic bandwidth required.
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+ *
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+ * @return 0 if successful, negative error code otherwise.
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+ */
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+static int check_periodic_bandwidth(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
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+static int find_single_uframe(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
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+{
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+ int status;
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+ uint16_t max_claimed_usecs;
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+ int i;
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+ u16 utime;
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+ int t_left;
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+ int ret;
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+ int done;
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+
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+ status = 0;
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+
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+ if (hcd->core_if->core_params->speed == DWC_SPEED_PARAM_HIGH) {
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+ /*
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+ * High speed mode.
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+ * Max periodic usecs is 80% x 125 usec = 100 usec.
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+ */
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+ max_claimed_usecs = 100 - qh->usecs;
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+ } else {
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+ /*
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+ * Full speed mode.
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+ * Max periodic usecs is 90% x 1000 usec = 900 usec.
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+ */
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+ max_claimed_usecs = 900 - qh->usecs;
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+ ret = -1;
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+ utime = qh->usecs;
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+ t_left = utime;
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+ i = 0;
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+ done = 0;
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+ while (done == 0) {
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+ /* At the start hcd->frame_usecs[i] = max_uframe_usecs[i]; */
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+ if (utime <= hcd->frame_usecs[i]) {
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+ hcd->frame_usecs[i] -= utime;
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+ qh->frame_usecs[i] += utime;
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+ t_left -= utime;
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+ ret = i;
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+ done = 1;
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+ return ret;
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+ } else {
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+ i++;
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+ if (i == 8) {
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+ done = 1;
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+ ret = -1;
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+ }
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+ }
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+ }
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+ return ret;
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+}
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+
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+ if (hcd->periodic_usecs > max_claimed_usecs) {
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+ DWC_NOTICE("%s: already claimed usecs %d, required usecs %d\n",
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+ __func__, hcd->periodic_usecs, qh->usecs);
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+ status = -ENOSPC;
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+/*
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+ * use this for FS apps that can span multiple uframes
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+ */
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+static int find_multi_uframe(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
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+{
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+ int i;
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+ int j;
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+ u16 utime;
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+ int t_left;
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+ int ret;
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+ int done;
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+ u16 xtime;
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+
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+ ret = -1;
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+ utime = qh->usecs;
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+ t_left = utime;
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+ i = 0;
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+ done = 0;
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+loop:
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+ while (done == 0) {
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+ if (hcd->frame_usecs[i] <= 0) {
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+ i++;
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+ if (i == 8) {
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+ done = 1;
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+ ret = -1;
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+ }
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+ goto loop;
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+ }
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+
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+ /*
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+ * We need n consequtive slots so use j as a start slot.
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+ * j plus j+1 must be enough time (for now)
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+ */
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+ xtime = hcd->frame_usecs[i];
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+ for (j = i + 1; j < 8; j++) {
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+ /*
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+ * if we add this frame remaining time to xtime we may
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+ * be OK, if not we need to test j for a complete frame.
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+ */
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+ if ((xtime + hcd->frame_usecs[j]) < utime) {
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+ if (hcd->frame_usecs[j] < max_uframe_usecs[j]) {
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+ j = 8;
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+ ret = -1;
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+ continue;
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+ }
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+ }
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+ if (xtime >= utime) {
|
||||
+ ret = i;
|
||||
+ j = 8; /* stop loop with a good value ret */
|
||||
+ continue;
|
||||
+ }
|
||||
+ /* add the frame time to x time */
|
||||
+ xtime += hcd->frame_usecs[j];
|
||||
+ /* we must have a fully available next frame or break */
|
||||
+ if ((xtime < utime) &&
|
||||
+ (hcd->frame_usecs[j] == max_uframe_usecs[j])) {
|
||||
+ ret = -1;
|
||||
+ j = 8; /* stop loop with a bad value ret */
|
||||
+ continue;
|
||||
+ }
|
||||
+ }
|
||||
+ if (ret >= 0) {
|
||||
+ t_left = utime;
|
||||
+ for (j = i; (t_left > 0) && (j < 8); j++) {
|
||||
+ t_left -= hcd->frame_usecs[j];
|
||||
+ if (t_left <= 0) {
|
||||
+ qh->frame_usecs[j] +=
|
||||
+ hcd->frame_usecs[j] + t_left;
|
||||
+ hcd->frame_usecs[j] = -t_left;
|
||||
+ ret = i;
|
||||
+ done = 1;
|
||||
+ } else {
|
||||
+ qh->frame_usecs[j] +=
|
||||
+ hcd->frame_usecs[j];
|
||||
+ hcd->frame_usecs[j] = 0;
|
||||
+ }
|
||||
+ }
|
||||
+ } else {
|
||||
+ i++;
|
||||
+ if (i == 8) {
|
||||
+ done = 1;
|
||||
+ ret = -1;
|
||||
+ }
|
||||
+ }
|
||||
+ }
|
||||
+ return ret;
|
||||
+}
|
||||
+
|
||||
+ return status;
|
||||
+static int find_uframe(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
|
||||
+{
|
||||
+ int ret = -1;
|
||||
+
|
||||
+ if (qh->speed == USB_SPEED_HIGH)
|
||||
+ /* if this is a hs transaction we need a full frame */
|
||||
+ ret = find_single_uframe(hcd, qh);
|
||||
+ else
|
||||
+ /* FS transaction may need a sequence of frames */
|
||||
+ ret = find_multi_uframe(hcd, qh);
|
||||
+
|
||||
+ return ret;
|
||||
+}
|
||||
+
|
||||
+/**
|
||||
@ -13467,58 +13578,55 @@
|
||||
+
|
||||
+/**
|
||||
+ * Schedules an interrupt or isochronous transfer in the periodic schedule.
|
||||
+ *
|
||||
+ * @param hcd The HCD state structure for the DWC OTG controller.
|
||||
+ * @param qh QH for the periodic transfer. The QH should already contain the
|
||||
+ * scheduling information.
|
||||
+ *
|
||||
+ * @return 0 if successful, negative error code otherwise.
|
||||
+ */
|
||||
+static int schedule_periodic(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
|
||||
+{
|
||||
+ int status = 0;
|
||||
+ int status;
|
||||
+ struct usb_bus *bus = hcd_to_bus(dwc_otg_hcd_to_hcd(hcd));
|
||||
+ int frame;
|
||||
+
|
||||
+ status = periodic_channel_available(hcd);
|
||||
+ status = find_uframe(hcd, qh);
|
||||
+ frame = -1;
|
||||
+ if (status == 0) {
|
||||
+ frame = 7;
|
||||
+ } else {
|
||||
+ if (status > 0)
|
||||
+ frame = status - 1;
|
||||
+ }
|
||||
+ /* Set the new frame up */
|
||||
+ if (frame > -1) {
|
||||
+ qh->sched_frame &= ~0x7;
|
||||
+ qh->sched_frame |= (frame & 7);
|
||||
+ }
|
||||
+ if (status != -1)
|
||||
+ status = 0;
|
||||
+ if (status) {
|
||||
+ DWC_NOTICE("%s: No host channel available for periodic "
|
||||
+ "transfer.\n", __func__);
|
||||
+ pr_notice("%s: Insufficient periodic bandwidth for "
|
||||
+ "periodic transfer.\n", __func__);
|
||||
+ return status;
|
||||
+ }
|
||||
+
|
||||
+ status = check_periodic_bandwidth(hcd, qh);
|
||||
+ if (status) {
|
||||
+ DWC_NOTICE("%s: Insufficient periodic bandwidth for "
|
||||
+ "periodic transfer.\n", __func__);
|
||||
+ return status;
|
||||
+ }
|
||||
+
|
||||
+ status = check_max_xfer_size(hcd, qh);
|
||||
+ if (status) {
|
||||
+ DWC_NOTICE("%s: Channel max transfer size too small "
|
||||
+ "for periodic transfer.\n", __func__);
|
||||
+ pr_notice("%s: Channel max transfer size too small "
|
||||
+ "for periodic transfer.\n", __func__);
|
||||
+ return status;
|
||||
+ }
|
||||
+
|
||||
+ /* Always start in the inactive schedule. */
|
||||
+ list_add_tail(&qh->qh_list_entry, &hcd->periodic_sched_inactive);
|
||||
+
|
||||
+ /* Reserve the periodic channel. */
|
||||
+ hcd->periodic_channels++;
|
||||
+
|
||||
+ /* Update claimed usecs per (micro)frame. */
|
||||
+ hcd->periodic_usecs += qh->usecs;
|
||||
+
|
||||
+ /* Update average periodic bandwidth claimed and # periodic reqs for usbfs. */
|
||||
+ hcd_to_bus(dwc_otg_hcd_to_hcd(hcd))->bandwidth_allocated += qh->usecs / qh->interval;
|
||||
+ if (qh->ep_type == USB_ENDPOINT_XFER_INT) {
|
||||
+ hcd_to_bus(dwc_otg_hcd_to_hcd(hcd))->bandwidth_int_reqs++;
|
||||
+ DWC_DEBUGPL(DBG_HCD, "Scheduled intr: qh %p, usecs %d, period %d\n",
|
||||
+ qh, qh->usecs, qh->interval);
|
||||
+ } else {
|
||||
+ hcd_to_bus(dwc_otg_hcd_to_hcd(hcd))->bandwidth_isoc_reqs++;
|
||||
+ DWC_DEBUGPL(DBG_HCD, "Scheduled isoc: qh %p, usecs %d, period %d\n",
|
||||
+ qh, qh->usecs, qh->interval);
|
||||
+ }
|
||||
+ /*
|
||||
+ * Update average periodic bandwidth claimed and # periodic reqs for
|
||||
+ * usbfs.
|
||||
+ */
|
||||
+ bus->bandwidth_allocated += qh->usecs / qh->interval;
|
||||
+
|
||||
+ if (qh->ep_type == USB_ENDPOINT_XFER_INT)
|
||||
+ bus->bandwidth_int_reqs++;
|
||||
+ else
|
||||
+ bus->bandwidth_isoc_reqs++;
|
||||
+
|
||||
+ return status;
|
||||
+}
|
||||
@ -13569,32 +13677,29 @@
|
||||
+
|
||||
+/**
|
||||
+ * Removes an interrupt or isochronous transfer from the periodic schedule.
|
||||
+ *
|
||||
+ * @param hcd The HCD state structure for the DWC OTG controller.
|
||||
+ * @param qh QH for the periodic transfer.
|
||||
+ */
|
||||
+static void deschedule_periodic(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
|
||||
+{
|
||||
+ struct usb_bus *bus = hcd_to_bus(dwc_otg_hcd_to_hcd(hcd));
|
||||
+ int i;
|
||||
+
|
||||
+ list_del_init(&qh->qh_list_entry);
|
||||
+
|
||||
+ /* Release the periodic channel reservation. */
|
||||
+ hcd->periodic_channels--;
|
||||
+
|
||||
+ /* Update claimed usecs per (micro)frame. */
|
||||
+ hcd->periodic_usecs -= qh->usecs;
|
||||
+
|
||||
+ /* Update average periodic bandwidth claimed and # periodic reqs for usbfs. */
|
||||
+ hcd_to_bus(dwc_otg_hcd_to_hcd(hcd))->bandwidth_allocated -= qh->usecs / qh->interval;
|
||||
+
|
||||
+ if (qh->ep_type == USB_ENDPOINT_XFER_INT) {
|
||||
+ hcd_to_bus(dwc_otg_hcd_to_hcd(hcd))->bandwidth_int_reqs--;
|
||||
+ DWC_DEBUGPL(DBG_HCD, "Descheduled intr: qh %p, usecs %d, period %d\n",
|
||||
+ qh, qh->usecs, qh->interval);
|
||||
+ } else {
|
||||
+ hcd_to_bus(dwc_otg_hcd_to_hcd(hcd))->bandwidth_isoc_reqs--;
|
||||
+ DWC_DEBUGPL(DBG_HCD, "Descheduled isoc: qh %p, usecs %d, period %d\n",
|
||||
+ qh, qh->usecs, qh->interval);
|
||||
+ for (i = 0; i < 8; i++) {
|
||||
+ hcd->frame_usecs[i] += qh->frame_usecs[i];
|
||||
+ qh->frame_usecs[i] = 0;
|
||||
+ }
|
||||
+ /*
|
||||
+ * Update average periodic bandwidth claimed and # periodic reqs for
|
||||
+ * usbfs.
|
||||
+ */
|
||||
+ bus->bandwidth_allocated -= qh->usecs / qh->interval;
|
||||
+
|
||||
+ if (qh->ep_type == USB_ENDPOINT_XFER_INT)
|
||||
+ bus->bandwidth_int_reqs--;
|
||||
+ else
|
||||
+ bus->bandwidth_isoc_reqs--;
|
||||
+}
|
||||
+
|
||||
+/**
|
||||
|
Loading…
Reference in New Issue
Block a user